Bipin Ravi 66bf3ba482 fix(cpus): workaround for Cortex-A78C erratum 2779484 ... Cortex-A78C erratum 2779484 is a Cat B erratum that applies to revisions r0p1 and r0p2 and is still open. The workaround is to set the CPUACTLR3_EL1[47] bit to 1. Setting this bit might have a small impact on power and negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/SDEN2004089/latest Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Change-Id: I9a8c16a845c3ba6eb2f17a5119aa6ca09a0d27ed		2023-03-08 22:00:14 +01:00
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aarch32	build: always prefix section names with .	2023-02-20 18:29:33 +00:00
aarch64	fix(cpus): workaround for Cortex-A78C erratum 2779484	2023-03-08 22:00:14 +01:00
errata_report.h	Workaround for Cortex A78 erratum 1951500	2021-01-13 13:54:18 -06:00
wa_cve_2017_5715.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2018_3639.h	Fix MISRA defects in workaround and errata framework	2018-10-29 14:41:48 +00:00
wa_cve_2022_23960.h	fix(security): apply SMCCC_ARCH_WORKAROUND_3 to A73/A75/A72/A57	2022-03-18 01:01:34 +02:00