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38f762a5ee
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
* This core has only errata related to DSU, which is defined under
another file dsu_helpers.s but gets applied to A65AE as well.
Hence symbolic names have been added to get them registered under
errata framework.
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Testing was conducted by:
* Building for release with all errata flags enabled and running
script in change 19136 to compare output of objdump for each errata.
* Testing via script was not complete, as it directed to verify the
check and the workaround functions of few erratas manually.
* Manual comparison of disassembly of converted functions with non-
converted functions
aarch64-none-elf-objdump -D <trusted-firmware-a with conversion>/build/../release/bl31/bl31.elf
vs
aarch64-none-elf-objdump -D <trusted-firmware-a clean repo>/build/fvp/release/bl31/bl31.elf
* Manual comparison of disassembly of both both files(bl31.elf)
ensured, the ported changes were identical and hence verified.
* Build for release with all errata flags enabled and run default
tftf tests.
CROSS_COMPILE=aarch64-none-elf- \
make PLAT=fvp \
ARCH=aarch64 \
DEBUG=0 \
HW_ASSISTED_COHERENCY=1 \
USE_COHERENT_MEM=0 \
CTX_INCLUDE_AARCH32_REGS=0 \
ERRATA_DSU_936184=1 \
BL33=/home/jaychi01/tf_a/tf-a-tests/build/fvp/release/tftf.bin \
fip all -j12
* Build for debug with all errata enabled and step through ArmDS
at reset to ensure that if Errata are applicable then the workaround
functions are entered precisely. In this case, errata is not
applied as DSU does not has the ACP interface and hence the
check_errata_dsu_936184 returns 0.
* In summary, porting work for this CPU, does not adds any new changes
as we are just creating macros via .equ, henceforth code remains
identical.
Change-Id: Iab37295319b5ccd69428185b2d22af0ca9c07a5e
Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>
58 lines
1.6 KiB
ArmAsm
58 lines
1.6 KiB
ArmAsm
/*
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* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <cortex_a65ae.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if !HW_ASSISTED_COHERENCY
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#error "Cortex-A65AE must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS
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#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/*
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* ERRATA_DSU_936184 :
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* The errata is defined in dsu_helpers.S but applies to cortex_a65ae
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* as well. Henceforth creating symbolic names to the already existing errata
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* workaround functions to get them registered under the Errata Framework.
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*/
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.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184
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.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa
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add_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
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cpu_reset_func_start cortex_a65ae
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cpu_reset_func_end cortex_a65ae
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func cortex_a65ae_cpu_pwr_dwn
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sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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isb
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ret
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endfunc cortex_a65ae_cpu_pwr_dwn
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errata_report_shim cortex_a65ae
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.section .rodata.cortex_a65ae_regs, "aS"
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cortex_a65ae_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a65ae_cpu_reg_dump
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adr x6, cortex_a65ae_regs
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mrs x8, CORTEX_A65AE_ECTLR_EL1
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ret
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endfunc cortex_a65ae_cpu_reg_dump
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declare_cpu_ops cortex_a65ae, CORTEX_A65AE_MIDR, \
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cortex_a65ae_reset_func, \
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cortex_a65ae_cpu_pwr_dwn
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