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cba71b70ef
Under specific conditions, the processor might issue an eviction and an L2 cache clean operation to the interconnect in the wrong order. Set the CPUACTLR.ENDCCASCI bit to 1 to avoid this. Change-Id: Ide7393adeae04581fa70eb9173b742049fc3e050 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
196 lines
4.7 KiB
ArmAsm
196 lines
4.7 KiB
ArmAsm
/*
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* Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a35.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* ---------------------------------------------
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* Disable L1 data cache and unified L2 cache
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* ---------------------------------------------
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*/
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func cortex_a35_disable_dcache
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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ret
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endfunc cortex_a35_disable_dcache
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* ---------------------------------------------
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*/
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func cortex_a35_disable_smp
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mrs x0, CORTEX_A35_CPUECTLR_EL1
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bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
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msr CORTEX_A35_CPUECTLR_EL1, x0
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isb
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dsb sy
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ret
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endfunc cortex_a35_disable_smp
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/* ---------------------------------------------------
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* Errata Workaround for Cortex A35 Errata #855472.
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* This applies to revisions r0p0 of Cortex A35.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* ---------------------------------------------------
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*/
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func errata_a35_855472_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_855472
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cbz x0, 1f
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mrs x1, CORTEX_A35_CPUACTLR_EL1
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orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
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msr CORTEX_A35_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a35_855472_wa
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func check_errata_855472
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_855472
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A35.
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* Clobbers: x0
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* -------------------------------------------------
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*/
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func cortex_a35_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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#if ERRATA_A35_855472
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bl errata_a35_855472_wa
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#endif
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A35_CPUECTLR_EL1
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orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
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msr CORTEX_A35_CPUECTLR_EL1, x0
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isb
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ret x19
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endfunc cortex_a35_reset_func
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func cortex_a35_core_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a35_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a35_disable_smp
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endfunc cortex_a35_core_pwr_dwn
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func cortex_a35_cluster_pwr_dwn
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mov x18, x30
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/* ---------------------------------------------
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* Turn off caches.
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* ---------------------------------------------
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*/
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bl cortex_a35_disable_dcache
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 caches.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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mov x30, x18
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b cortex_a35_disable_smp
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endfunc cortex_a35_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A35. Must follow AAPCS.
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*/
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func cortex_a35_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A35_855472, cortex_a35, 855472
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a35_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a35 specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a35_regs, "aS"
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cortex_a35_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a35_cpu_reg_dump
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adr x6, cortex_a35_regs
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mrs x8, CORTEX_A35_CPUECTLR_EL1
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ret
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endfunc cortex_a35_cpu_reg_dump
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declare_cpu_ops cortex_a35, CORTEX_A35_MIDR, \
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cortex_a35_reset_func, \
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cortex_a35_core_pwr_dwn, \
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cortex_a35_cluster_pwr_dwn
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