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ef430ff495
This patch fixes FVP_Base_AEMv8A model hang issue with ARMv8.4+ with cache modelling enabled configuration. Incorrect L1 cache flush operation to PoU, using CLIDR_EL1 LoUIS field, which is required by the architecture to be zero for ARMv8.4-A with ARMv8.4-S2FWB feature is replaced with L1 to L2 and L2 to L3 (if L3 is present) cache flushes. FVP_Base_AEMv8A model can be configured with L3 enabled by setting `cluster0.l3cache-size` and `cluster1.l3cache-size` to non-zero values, and presence of L3 is checked in `aem_generic_core_pwr_dwn` function by reading CLIDR_EL1.Ctype3 field value. Change-Id: If3de3d4eb5ed409e5b4ccdbc2fe6d5a01894a9af Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
113 lines
2.9 KiB
ArmAsm
113 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2014-2019, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <aem_generic.h>
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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func aem_generic_core_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* AEM model supports L3 caches in which case L2
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* will be private per core caches and flush
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* from L1 to L2 is not sufficient.
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* ---------------------------------------------
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*/
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mrs x1, clidr_el1
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/* ---------------------------------------------
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* Check if L3 cache is implemented.
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* ---------------------------------------------
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*/
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tst x1, ((1 << CLIDR_FIELD_WIDTH) - 1) << CTYPE_SHIFT(3)
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/* ---------------------------------------------
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* There is no L3 cache, flush L1 to L2 only.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b.eq dcsw_op_level1
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mov x18, x30
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/* ---------------------------------------------
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* Flush L1 cache to L2.
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* ---------------------------------------------
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*/
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bl dcsw_op_level1
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mov x30, x18
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/* ---------------------------------------------
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* Flush L2 cache to L3.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b dcsw_op_level2
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endfunc aem_generic_core_pwr_dwn
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func aem_generic_cluster_pwr_dwn
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/* ---------------------------------------------
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* Disable the Data Cache.
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* ---------------------------------------------
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*/
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mrs x1, sctlr_el3
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bic x1, x1, #SCTLR_C_BIT
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msr sctlr_el3, x1
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isb
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/* ---------------------------------------------
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* Flush all caches to PoC.
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* ---------------------------------------------
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*/
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mov x0, #DCCISW
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b dcsw_op_all
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endfunc aem_generic_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for AEM. Must follow AAPCS.
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*/
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func aem_generic_errata_report
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ret
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endfunc aem_generic_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cpu specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.aem_generic_regs, "aS"
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aem_generic_regs: /* The ascii list of register names to be reported */
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.asciz "" /* no registers to report */
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func aem_generic_cpu_reg_dump
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adr x6, aem_generic_regs
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ret
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endfunc aem_generic_cpu_reg_dump
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/* cpu_ops for Base AEM FVP */
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declare_cpu_ops aem_generic, BASE_AEM_MIDR, CPU_NO_RESET_FUNC, \
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aem_generic_core_pwr_dwn, \
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aem_generic_cluster_pwr_dwn
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/* cpu_ops for Foundation FVP */
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declare_cpu_ops aem_generic, FOUNDATION_AEM_MIDR, CPU_NO_RESET_FUNC, \
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aem_generic_core_pwr_dwn, \
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aem_generic_cluster_pwr_dwn
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