mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
6578343bb2
Add basic CPU library code to support the Blackhawk CPU, BlackHawk core is based out of Hunter ELP core, so overall library code was adapted based on that. Change-Id: I4750e774732218ee669dceb734cd107f46b78492 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
77 lines
2.2 KiB
ArmAsm
77 lines
2.2 KiB
ArmAsm
/*
|
|
* Copyright (c) 2023, Arm Limited. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <arch.h>
|
|
#include <asm_macros.S>
|
|
#include <common/bl_common.h>
|
|
#include <cortex_blackhawk.h>
|
|
#include <cpu_macros.S>
|
|
#include <plat_macros.S>
|
|
|
|
/* Hardware handled coherency */
|
|
#if HW_ASSISTED_COHERENCY == 0
|
|
#error "Cortex blackhawk must be compiled with HW_ASSISTED_COHERENCY enabled"
|
|
#endif
|
|
|
|
/* 64-bit only core */
|
|
#if CTX_INCLUDE_AARCH32_REGS == 1
|
|
#error "Cortex blackhawk supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
|
|
#endif
|
|
|
|
func cortex_blackhawk_reset_func
|
|
/* Disable speculative loads */
|
|
msr SSBS, xzr
|
|
isb
|
|
ret
|
|
endfunc cortex_blackhawk_reset_func
|
|
|
|
/* ----------------------------------------------------
|
|
* HW will do the cache maintenance while powering down
|
|
* ----------------------------------------------------
|
|
*/
|
|
func cortex_blackhawk_core_pwr_dwn
|
|
/* ---------------------------------------------------
|
|
* Enable CPU power down bit in power control register
|
|
* ---------------------------------------------------
|
|
*/
|
|
mrs x0, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1
|
|
orr x0, x0, #CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
|
|
msr CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, x0
|
|
isb
|
|
ret
|
|
endfunc cortex_blackhawk_core_pwr_dwn
|
|
|
|
#if REPORT_ERRATA
|
|
/*
|
|
* Errata printing function for Cortex Blackhawk. Must follow AAPCS.
|
|
*/
|
|
func cortex_blackhawk_errata_report
|
|
ret
|
|
endfunc cortex_blackhawk_errata_report
|
|
#endif
|
|
|
|
/* ---------------------------------------------
|
|
* This function provides Cortex Blackhawk specific
|
|
* register information for crash reporting.
|
|
* It needs to return with x6 pointing to
|
|
* a list of register names in ascii and
|
|
* x8 - x15 having values of registers to be
|
|
* reported.
|
|
* ---------------------------------------------
|
|
*/
|
|
.section .rodata.cortex_blackhawk_regs, "aS"
|
|
cortex_blackhawk_regs: /* The ascii list of register names to be reported */
|
|
.asciz "cpuectlr_el1", ""
|
|
|
|
func cortex_blackhawk_cpu_reg_dump
|
|
adr x6, cortex_blackhawk_regs
|
|
mrs x8, CORTEX_BLACKHAWK_CPUECTLR_EL1
|
|
ret
|
|
endfunc cortex_blackhawk_cpu_reg_dump
|
|
|
|
declare_cpu_ops cortex_blackhawk, CORTEX_BLACKHAWK_MIDR, \
|
|
cortex_blackhawk_reset_func, \
|
|
cortex_blackhawk_core_pwr_dwn
|