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6512c3a62a
The IDC register from DBGMCU is duplicated in SYSCFG. As SYSCFG is always accessible, get chip ID and revision ID from there on STM32MP13. Change-Id: Ib0b6e8f68a2934a45ec0012f69db6c12a60adb17 Signed-off-by: Yann Gautier <yann.gautier@st.com>
255 lines
6.5 KiB
C
255 lines
6.5 KiB
C
/*
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* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/clk.h>
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#include <drivers/delay_timer.h>
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#include <drivers/st/stpmic1.h>
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#include <lib/mmio.h>
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#include <lib/utils_def.h>
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#include <platform_def.h>
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#include <stm32mp_common.h>
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#include <stm32mp_dt.h>
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#include <stm32mp1_private.h>
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/*
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* SYSCFG REGISTER OFFSET (base relative)
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*/
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#define SYSCFG_BOOTR 0x00U
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#if STM32MP15
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#define SYSCFG_IOCTRLSETR 0x18U
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#define SYSCFG_ICNR 0x1CU
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#endif
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#define SYSCFG_CMPCR 0x20U
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#define SYSCFG_CMPENSETR 0x24U
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#define SYSCFG_CMPENCLRR 0x28U
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#define SYSCFG_IDC 0x380U
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#define CMPCR_CMPENSETR_OFFSET 0x4U
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#define CMPCR_CMPENCLRR_OFFSET 0x8U
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/*
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* SYSCFG_BOOTR Register
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*/
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#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
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#if STM32MP15
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#define SYSCFG_BOOTR_BOOTPD_MASK GENMASK(6, 4)
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#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
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#endif
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/*
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* SYSCFG_IOCTRLSETR Register
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*/
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#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
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#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
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#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
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/*
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* SYSCFG_ICNR Register
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*/
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#define SYSCFG_ICNR_AXI_M9 BIT(9)
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/*
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* SYSCFG_CMPCR Register
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*/
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#define SYSCFG_CMPCR_SW_CTRL BIT(1)
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#define SYSCFG_CMPCR_READY BIT(8)
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#define SYSCFG_CMPCR_RANSRC GENMASK(19, 16)
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#define SYSCFG_CMPCR_RANSRC_SHIFT 16
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#define SYSCFG_CMPCR_RAPSRC GENMASK(23, 20)
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#define SYSCFG_CMPCR_ANSRC_SHIFT 24
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#define SYSCFG_CMPCR_READY_TIMEOUT_US 10000U
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/*
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* SYSCFG_CMPENSETR Register
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*/
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#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
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/*
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* SYSCFG_IDC Register
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*/
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#define SYSCFG_IDC_DEV_ID_MASK GENMASK(11, 0)
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#define SYSCFG_IDC_REV_ID_MASK GENMASK(31, 16)
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#define SYSCFG_IDC_REV_ID_SHIFT 16
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static void enable_io_comp_cell_finish(uintptr_t cmpcr_off)
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{
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uint64_t start;
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start = timeout_init_us(SYSCFG_CMPCR_READY_TIMEOUT_US);
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while ((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) {
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if (timeout_elapsed(start)) {
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/* Failure on IO compensation enable is not a issue: warn only. */
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WARN("IO compensation cell not ready\n");
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break;
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}
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}
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mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_SW_CTRL);
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}
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static void disable_io_comp_cell(uintptr_t cmpcr_off)
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{
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uint32_t value;
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if (((mmio_read_32(SYSCFG_BASE + cmpcr_off) & SYSCFG_CMPCR_READY) == 0U) ||
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((mmio_read_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENSETR_OFFSET) &
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SYSCFG_CMPENSETR_MPU_EN) == 0U)) {
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return;
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}
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value = mmio_read_32(SYSCFG_BASE + cmpcr_off) >> SYSCFG_CMPCR_ANSRC_SHIFT;
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mmio_clrbits_32(SYSCFG_BASE + cmpcr_off, SYSCFG_CMPCR_RANSRC | SYSCFG_CMPCR_RAPSRC);
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value <<= SYSCFG_CMPCR_RANSRC_SHIFT;
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value |= mmio_read_32(SYSCFG_BASE + cmpcr_off);
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mmio_write_32(SYSCFG_BASE + cmpcr_off, value | SYSCFG_CMPCR_SW_CTRL);
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mmio_setbits_32(SYSCFG_BASE + cmpcr_off + CMPCR_CMPENCLRR_OFFSET, SYSCFG_CMPENSETR_MPU_EN);
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}
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static void enable_high_speed_mode_low_voltage(void)
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{
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#if STM32MP15
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mmio_write_32(SYSCFG_BASE + SYSCFG_IOCTRLSETR,
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SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
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SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
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SYSCFG_IOCTRLSETR_HSLVEN_ETH |
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SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
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SYSCFG_IOCTRLSETR_HSLVEN_SPI);
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#endif
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}
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static void stm32mp1_syscfg_set_hslv(void)
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{
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uint32_t otp_value;
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uint32_t vdd_voltage;
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bool product_below_2v5;
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/*
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* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
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* and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
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* It could be disabled for low frequencies or if AFMUX is selected
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* but the function is not used, typically for TRACE.
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* If high speed low voltage pad mode is node enable, platform will
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* over consume.
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*
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* WARNING:
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* Enabling High Speed mode while VDD > 2.7V
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* with the OTP product_below_2v5 (OTP 18, BIT 13)
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* erroneously set to 1 can damage the SoC!
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* => TF-A enables the low power mode only if VDD < 2.7V (in DT)
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* but this value needs to be consistent with board design.
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*/
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if (stm32_get_otp_value(HW2_OTP, &otp_value) != 0) {
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panic();
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}
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product_below_2v5 = (otp_value & HW2_OTP_PRODUCT_BELOW_2V5) != 0U;
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/* Get VDD supply */
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vdd_voltage = dt_get_pwr_vdd_voltage();
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/* Check if VDD is Low Voltage */
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if (vdd_voltage == 0U) {
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WARN("VDD unknown\n");
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} else if (vdd_voltage < 2700000U) {
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enable_high_speed_mode_low_voltage();
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if (!product_below_2v5) {
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INFO("Product_below_2v5=0: HSLVEN protected by HW\n");
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}
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} else {
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if (product_below_2v5) {
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ERROR("Product_below_2v5=1:\n");
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ERROR("\tHSLVEN update is destructive,\n");
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ERROR("\tno update as VDD > 2.7V\n");
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panic();
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}
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}
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}
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void stm32mp1_syscfg_init(void)
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{
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#if STM32MP15
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uint32_t bootr;
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/*
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* Interconnect update : select master using the port 1.
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* LTDC = AXI_M9.
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*/
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mmio_write_32(SYSCFG_BASE + SYSCFG_ICNR, SYSCFG_ICNR_AXI_M9);
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/* Disable Pull-Down for boot pin connected to VDD */
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bootr = mmio_read_32(SYSCFG_BASE + SYSCFG_BOOTR) &
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SYSCFG_BOOTR_BOOT_MASK;
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mmio_clrsetbits_32(SYSCFG_BASE + SYSCFG_BOOTR, SYSCFG_BOOTR_BOOTPD_MASK,
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bootr << SYSCFG_BOOTR_BOOTPD_SHIFT);
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#endif
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stm32mp1_syscfg_set_hslv();
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stm32mp1_syscfg_enable_io_compensation_start();
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}
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void stm32mp1_syscfg_enable_io_compensation_start(void)
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{
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/*
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* Activate automatic I/O compensation.
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* Warning: need to ensure CSI enabled and ready in clock driver.
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* Enable non-secure clock, we assume non-secure is suspended.
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*/
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clk_enable(SYSCFG);
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mmio_setbits_32(SYSCFG_BASE + CMPCR_CMPENSETR_OFFSET + SYSCFG_CMPCR,
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SYSCFG_CMPENSETR_MPU_EN);
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}
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void stm32mp1_syscfg_enable_io_compensation_finish(void)
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{
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enable_io_comp_cell_finish(SYSCFG_CMPCR);
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}
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void stm32mp1_syscfg_disable_io_compensation(void)
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{
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clk_enable(SYSCFG);
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/*
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* Deactivate automatic I/O compensation.
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* Warning: CSI is disabled automatically in STOP if not
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* requested for other usages and always OFF in STANDBY.
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* Disable non-secure SYSCFG clock, we assume non-secure is suspended.
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*/
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disable_io_comp_cell(SYSCFG_CMPCR);
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clk_disable(SYSCFG);
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}
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/*
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* @brief Get silicon revision from SYSCFG registers.
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* @retval chip version (REV_ID).
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*/
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uint32_t stm32mp1_syscfg_get_chip_version(void)
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{
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return (mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) &
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SYSCFG_IDC_REV_ID_MASK) >> SYSCFG_IDC_REV_ID_SHIFT;
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}
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/*
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* @brief Get device ID from SYSCFG registers.
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* @retval device ID (DEV_ID).
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*/
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uint32_t stm32mp1_syscfg_get_chip_dev_id(void)
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{
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return mmio_read_32(SYSCFG_BASE + SYSCFG_IDC) & SYSCFG_IDC_DEV_ID_MASK;
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}
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