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Madhukar Pappireddy 83e955241a Workaround for Hercules erratum 1688305 
Erratum 1688305 is a Cat B erratum present in r0p0, r0p1 versions
of Hercules core. The erratum can be avoided by setting bit 1 of the
implementation defined register CPUACTLR2_EL1 to 1 to prevent store-
release from being dispatched before it is the oldest.

Change-Id: I2ac04f5d9423868b6cdd4ceb3d0ffa46e570efed
Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
2019-12-23 11:21:16 -06:00
..
alt-boot-flows.rst doc: Split the User Guide into multiple files 2019-11-27 10:45:54 +00:00
auth-framework.rst doc: Convert internal links to RST format 2019-10-08 15:58:03 +00:00
cpu-specific-build-macros.rst Workaround for Hercules erratum 1688305 2019-12-23 11:21:16 -06:00
firmware-design.rst Merge "Changes to support updated register usage in SMCCC v1.2" into integration 2019-11-29 10:06:37 +00:00
index.rst doc: Split the User Guide into multiple files 2019-11-27 10:45:54 +00:00
interrupt-framework-design.rst doc: Convert internal links to RST format 2019-10-08 15:58:03 +00:00
psci-pd-tree.rst doc: Set correct syntax highlighting style 2019-05-22 11:28:17 +01:00
reset-design.rst doc: Split the User Guide into multiple files 2019-11-27 10:45:54 +00:00
trusted-board-boot-build.rst doc: Split the User Guide into multiple files 2019-11-27 10:45:54 +00:00
trusted-board-boot.rst doc: Split the User Guide into multiple files 2019-11-27 10:45:54 +00:00