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Having an active stack while enabling MMU has shown coherency problems. This patch builds on top of translation library changes that introduces MMU-enabling without using stacks. Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. NOTE: Since this feature depends on using translation table library v2, disallow using translation table library v1 with HW_ASSISTED_COHERENCY. Fixes ARM-software/tf-issues#566 Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
188 lines
5.6 KiB
ArmAsm
188 lines
5.6 KiB
ArmAsm
/*
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* Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <console.h>
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#include <platform_def.h>
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.weak plat_report_exception
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.weak plat_crash_console_init
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.weak plat_crash_console_putc
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.weak plat_crash_console_flush
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.weak plat_reset_handler
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.weak plat_disable_acp
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.weak bl1_plat_prepare_exit
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.weak plat_panic_handler
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.weak bl31_plat_enable_mmu
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.weak bl32_plat_enable_mmu
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#if !ENABLE_PLAT_COMPAT
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.globl platform_get_core_pos
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#define MPIDR_RES_BIT_MASK 0xff000000
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/* ------------------------------------------------------------------
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* int platform_get_core_pos(int mpidr)
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* Returns the CPU index of the CPU specified by mpidr. This is
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* defined when platform compatibility is disabled to enable Trusted
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* Firmware components like SPD using the old platform API to work.
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* This API is deprecated and it assumes that the mpidr specified is
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* that of a valid and present CPU. Instead, plat_my_core_pos()
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* should be used for CPU index of the current CPU and
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* plat_core_pos_by_mpidr() should be used for CPU index of a
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* CPU specified by its mpidr.
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* ------------------------------------------------------------------
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*/
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func_deprecated platform_get_core_pos
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bic x0, x0, #MPIDR_RES_BIT_MASK
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mrs x1, mpidr_el1
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bic x1, x1, #MPIDR_RES_BIT_MASK
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cmp x0, x1
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beq plat_my_core_pos
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b platform_core_pos_helper
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endfunc_deprecated platform_get_core_pos
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#endif
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/* -----------------------------------------------------
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* Placeholder function which should be redefined by
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* each platform.
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* -----------------------------------------------------
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*/
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func plat_report_exception
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ret
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endfunc plat_report_exception
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#if MULTI_CONSOLE_API
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/* -----------------------------------------------------
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* int plat_crash_console_init(void)
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* Use normal console by default. Switch it to crash
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* mode so serial consoles become active again.
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* NOTE: This default implementation will only work for
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* crashes that occur after a normal console (marked
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* valid for the crash state) has been registered with
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* the console framework. To debug crashes that occur
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* earlier, the platform has to override these functions
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* with an implementation that initializes a console
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* driver with hardcoded parameters. See
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* docs/porting-guide.rst for more information.
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* -----------------------------------------------------
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*/
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func plat_crash_console_init
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#if defined(IMAGE_BL1)
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/*
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* BL1 code can possibly crash so early that the data segment is not yet
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* accessible. Don't risk undefined behavior by trying to run the normal
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* console framework. Platforms that want to debug BL1 will need to
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* override this with custom functions that can run from registers only.
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*/
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mov x0, #0
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ret
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#else /* IMAGE_BL1 */
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mov x3, x30
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mov x0, #CONSOLE_FLAG_CRASH
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bl console_switch_state
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mov x0, #1
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ret x3
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#endif
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endfunc plat_crash_console_init
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/* -----------------------------------------------------
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* void plat_crash_console_putc(int character)
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* Output through the normal console by default.
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* -----------------------------------------------------
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*/
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func plat_crash_console_putc
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b console_putc
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endfunc plat_crash_console_putc
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/* -----------------------------------------------------
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* void plat_crash_console_flush(void)
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* Flush normal console by default.
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* -----------------------------------------------------
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*/
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func plat_crash_console_flush
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b console_flush
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endfunc plat_crash_console_flush
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#else /* MULTI_CONSOLE_API */
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/* -----------------------------------------------------
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* In the old API these are all no-op stubs that need to
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* be overridden by the platform to be useful.
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* -----------------------------------------------------
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*/
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func plat_crash_console_init
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mov x0, #0
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ret
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endfunc plat_crash_console_init
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func plat_crash_console_putc
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ret
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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ret
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endfunc plat_crash_console_flush
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#endif
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/* -----------------------------------------------------
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* Placeholder function which should be redefined by
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* each platform. This function should preserve x19 - x29.
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* -----------------------------------------------------
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*/
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func plat_reset_handler
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ret
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endfunc plat_reset_handler
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/* -----------------------------------------------------
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* Placeholder function which should be redefined by
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* each platform. This function is allowed to use
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* registers x0 - x17.
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* -----------------------------------------------------
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*/
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func plat_disable_acp
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ret
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endfunc plat_disable_acp
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/* -----------------------------------------------------
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* void bl1_plat_prepare_exit(entry_point_info_t *ep_info);
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* Called before exiting BL1. Default: do nothing
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* -----------------------------------------------------
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*/
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func bl1_plat_prepare_exit
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ret
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endfunc bl1_plat_prepare_exit
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/* -----------------------------------------------------
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* void plat_panic_handler(void) __dead2;
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* Endless loop by default.
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* -----------------------------------------------------
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*/
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func plat_panic_handler
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wfi
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b plat_panic_handler
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endfunc plat_panic_handler
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/* -----------------------------------------------------
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* void bl31_plat_enable_mmu(uint32_t flags);
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*
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* Enable MMU in BL31.
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* -----------------------------------------------------
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*/
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func bl31_plat_enable_mmu
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b enable_mmu_direct_el3
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endfunc bl31_plat_enable_mmu
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/* -----------------------------------------------------
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* void bl32_plat_enable_mmu(uint32_t flags);
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*
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* Enable MMU in BL32.
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* -----------------------------------------------------
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*/
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func bl32_plat_enable_mmu
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b enable_mmu_direct_el1
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endfunc bl32_plat_enable_mmu
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