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https://github.com/ARM-software/arm-trusted-firmware.git
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626ed510f1
This patch reworks the crash reporting mechanism to further optimise the stack and code size. The reporting makes use of assembly console functions to avoid calling C Runtime to report the CPU state. The crash buffer requirement is reduced to 64 bytes with this implementation. The crash buffer is now part of per-cpu data which makes retrieving the crash buffer trivial. Also now panic() will use crash reporting if invoked from BL3-1. Fixes ARM-software/tf-issues#199 Change-Id: I79d27a4524583d723483165dc40801f45e627da5
81 lines
2.7 KiB
ArmAsm
81 lines
2.7 KiB
ArmAsm
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <gic_v2.h>
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#include <plat_config.h>
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.section .rodata.gic_reg_name, "aS"
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gic_regs:
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.asciz "gic_hppir", "gic_ahppir", "gic_ctlr", ""
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gicd_pend_reg:
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.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
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newline:
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.asciz "\n"
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spacer:
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.asciz ":\t\t0x"
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/* ---------------------------------------------
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* The below macro prints out relevant GIC
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* registers whenever an unhandled exception is
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* taken in BL31.
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* Clobbers: x0 - x10, x16, sp
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* ---------------------------------------------
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*/
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.macro plat_print_gic_regs
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adr x0, plat_config
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ldr w16, [x0, #CONFIG_GICC_BASE_OFFSET]
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cbz x16, 1f
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/* gic base address is now in x16 */
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adr x6, gic_regs /* Load the gic reg list to x6 */
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/* Load the gic regs to gp regs used by str_in_crash_buf_print */
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ldr w8, [x16, #GICC_HPPIR]
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ldr w9, [x16, #GICC_AHPPIR]
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ldr w10, [x16, #GICC_CTLR]
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/* Store to the crash buf and print to cosole */
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bl str_in_crash_buf_print
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/* Print the GICD_ISPENDR regs */
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add x7, x16, #GICD_ISPENDR
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adr x4, gicd_pend_reg
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bl asm_print_str
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2:
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sub x4, x7, x16
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cmp x4, #0x280
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b.eq 1f
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bl asm_print_hex
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adr x4, spacer
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bl asm_print_str
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ldr x4, [x7], #8
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bl asm_print_hex
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adr x4, newline
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bl asm_print_str
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b 2b
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1:
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.endm
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