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https://github.com/ARM-software/arm-trusted-firmware.git
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e2ae6ceccc
Enable the MMU and add two entries to map the BL31 code and data regions. Additional mappings will be added dynamically, enhancing flexibility and modularity during the porting process. Change-Id: I333c34c58274a115f62f54730bba5b71165e3e36 Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
115 lines
2.3 KiB
C
115 lines
2.3 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <common/debug.h>
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#include <drivers/arm/gicv3.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <plat_console.h>
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#include <s32cc-bl-common.h>
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static entry_point_info_t bl33_image_ep_info;
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static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr);
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static uint32_t get_spsr_for_bl33_entry(void)
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{
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unsigned long mode = MODE_EL1;
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uint32_t spsr;
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spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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SET_PARAM_HEAD(&bl33_image_ep_info, PARAM_EP, VERSION_1, 0);
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bl33_image_ep_info.pc = BL33_BASE;
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bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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}
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void bl31_plat_arch_setup(void)
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{
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int ret;
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ret = s32cc_bl_mmu_setup();
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if (ret != 0) {
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panic();
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}
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console_s32g2_register();
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}
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struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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return &bl33_image_ep_info;
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}
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static int mmap_gic(const gicv3_driver_data_t *gic_data)
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{
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size_t gicr_size;
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int ret;
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ret = mmap_add_dynamic_region(gic_data->gicd_base,
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gic_data->gicd_base,
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PAGE_SIZE_64KB,
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MT_DEVICE | MT_RW | MT_SECURE);
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if (ret != 0) {
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return ret;
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}
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gicr_size = gicv3_redist_size(0x0U);
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ret = mmap_add_dynamic_region(gic_data->gicr_base,
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gic_data->gicr_base,
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gicr_size * gic_data->rdistif_num,
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MT_DEVICE | MT_RW | MT_SECURE);
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if (ret != 0) {
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return ret;
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}
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return 0;
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}
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void bl31_platform_setup(void)
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{
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static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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static gicv3_driver_data_t plat_gic_data = {
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.gicd_base = PLAT_GICD_BASE,
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.gicr_base = PLAT_GICR_BASE,
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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.mpidr_to_core_pos = s32g2_mpidr_to_core_pos,
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};
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unsigned int pos = plat_my_core_pos();
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int ret;
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ret = mmap_gic(&plat_gic_data);
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if (ret != 0) {
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panic();
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}
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gicv3_driver_init(&plat_gic_data);
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gicv3_distif_init();
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gicv3_rdistif_init(pos);
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gicv3_cpuif_enable(pos);
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}
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static unsigned int s32g2_mpidr_to_core_pos(unsigned long mpidr)
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{
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int core;
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core = plat_core_pos_by_mpidr(mpidr);
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if (core < 0) {
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return 0;
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}
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return (unsigned int)core;
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}
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