mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-17 01:54:22 +00:00
d55a445069
API documentation updated. Change-Id: I40feec1fe67a960d035061b54dd55610bc34ce1d Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
333 lines
11 KiB
C
333 lines
11 KiB
C
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __ARCH_HELPERS_H__
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#define __ARCH_HELPERS_H__
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#include <arch.h> /* for additional register definitions */
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#include <stdint.h>
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#include <sys/types.h>
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/**********************************************************************
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* Macros which create inline functions to read or write CPU system
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* registers
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*********************************************************************/
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#define _DEFINE_COPROCR_WRITE_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
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static inline void write_## _name(u_register_t v) \
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{ \
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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}
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#define _DEFINE_COPROCR_READ_FUNC(_name, coproc, opc1, CRn, CRm, opc2) \
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static inline u_register_t read_ ## _name(void) \
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{ \
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u_register_t v; \
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__asm__ volatile ("mrc "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : "=r" (v));\
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return v; \
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}
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/*
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* The undocumented %Q and %R extended asm are used to implemented the below
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* 64 bit `mrrc` and `mcrr` instructions. It works only on Little Endian
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* systems for GCC versions < 4.6. Above GCC 4.6, both Little Endian and
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* Big Endian systems generate the right instruction encoding.
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*/
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#if !(__clang__ || __GNUC__ > (4) || __GNUC__ == (4) && __GNUC_MINOR__ >= (6))
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#error "clang or GCC 4.6 or above is required to build AArch32 Trusted Firmware"
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#endif
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#define _DEFINE_COPROCR_WRITE_FUNC_64(_name, coproc, opc1, CRm) \
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static inline void write64_## _name(uint64_t v) \
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{ \
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__asm__ volatile ("mcrr "#coproc","#opc1", %Q0, %R0,"#CRm : : "r" (v));\
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}
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#define _DEFINE_COPROCR_READ_FUNC_64(_name, coproc, opc1, CRm) \
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static inline uint64_t read64_## _name(void) \
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{ uint64_t v; \
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__asm__ volatile ("mrrc "#coproc","#opc1", %Q0, %R0,"#CRm : "=r" (v));\
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return v; \
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}
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#define _DEFINE_SYSREG_READ_FUNC(_name, _reg_name) \
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static inline u_register_t read_ ## _name(void) \
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{ \
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u_register_t v; \
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__asm__ volatile ("mrs %0, " #_reg_name : "=r" (v)); \
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return v; \
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}
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#define _DEFINE_SYSREG_WRITE_FUNC(_name, _reg_name) \
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static inline void write_ ## _name(u_register_t v) \
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{ \
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__asm__ volatile ("msr " #_reg_name ", %0" : : "r" (v)); \
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}
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#define _DEFINE_SYSREG_WRITE_CONST_FUNC(_name, _reg_name) \
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static inline void write_ ## _name(const u_register_t v) \
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{ \
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__asm__ volatile ("msr " #_reg_name ", %0" : : "i" (v)); \
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}
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/* Define read function for coproc register */
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#define DEFINE_COPROCR_READ_FUNC(_name, ...) \
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_DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__)
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/* Define read & write function for coproc register */
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#define DEFINE_COPROCR_RW_FUNCS(_name, ...) \
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_DEFINE_COPROCR_READ_FUNC(_name, __VA_ARGS__) \
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_DEFINE_COPROCR_WRITE_FUNC(_name, __VA_ARGS__)
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/* Define 64 bit read function for coproc register */
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#define DEFINE_COPROCR_READ_FUNC_64(_name, ...) \
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_DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__)
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/* Define 64 bit read & write function for coproc register */
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#define DEFINE_COPROCR_RW_FUNCS_64(_name, ...) \
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_DEFINE_COPROCR_READ_FUNC_64(_name, __VA_ARGS__) \
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_DEFINE_COPROCR_WRITE_FUNC_64(_name, __VA_ARGS__)
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/* Define read & write function for system register */
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#define DEFINE_SYSREG_RW_FUNCS(_name) \
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_DEFINE_SYSREG_READ_FUNC(_name, _name) \
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_DEFINE_SYSREG_WRITE_FUNC(_name, _name)
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/**********************************************************************
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* Macros to create inline functions for tlbi operations
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*********************************************************************/
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#if ERRATA_A57_813419
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/*
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* Define function for TLBI instruction with type specifier that
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* implements the workaround for errata 813419 of Cortex-A57
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*/
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#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
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static inline void tlbi##_op(void) \
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{ \
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u_register_t v = 0; \
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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__asm__ volatile ("dsb ish");\
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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}
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#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
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static inline void tlbi##_op(u_register_t v) \
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{ \
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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__asm__ volatile ("dsb ish");\
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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}
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#else
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#define _DEFINE_TLBIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
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static inline void tlbi##_op(void) \
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{ \
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u_register_t v = 0; \
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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}
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#define _DEFINE_TLBIOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
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static inline void tlbi##_op(u_register_t v) \
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{ \
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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}
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#endif /* ERRATA_A57_813419 */
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#define _DEFINE_BPIOP_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
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static inline void bpi##_op(void) \
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{ \
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u_register_t v = 0; \
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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}
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/* Define function for simple TLBI operation */
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#define DEFINE_TLBIOP_FUNC(_op, ...) \
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_DEFINE_TLBIOP_FUNC(_op, __VA_ARGS__)
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/* Define function for TLBI operation with register parameter */
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#define DEFINE_TLBIOP_PARAM_FUNC(_op, ...) \
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_DEFINE_TLBIOP_PARAM_FUNC(_op, __VA_ARGS__)
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/* Define function for simple BPI operation */
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#define DEFINE_BPIOP_FUNC(_op, ...) \
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_DEFINE_BPIOP_FUNC(_op, __VA_ARGS__)
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/**********************************************************************
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* Macros to create inline functions for DC operations
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*********************************************************************/
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#define _DEFINE_DCOP_PARAM_FUNC(_op, coproc, opc1, CRn, CRm, opc2) \
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static inline void dc##_op(u_register_t v) \
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{ \
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__asm__ volatile ("mcr "#coproc","#opc1",%0,"#CRn","#CRm","#opc2 : : "r" (v));\
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}
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/* Define function for DC operation with register parameter */
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#define DEFINE_DCOP_PARAM_FUNC(_op, ...) \
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_DEFINE_DCOP_PARAM_FUNC(_op, __VA_ARGS__)
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/**********************************************************************
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* Macros to create inline functions for system instructions
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*********************************************************************/
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/* Define function for simple system instruction */
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#define DEFINE_SYSOP_FUNC(_op) \
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static inline void _op(void) \
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{ \
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__asm__ (#_op); \
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}
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/* Define function for system instruction with type specifier */
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#define DEFINE_SYSOP_TYPE_FUNC(_op, _type) \
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static inline void _op ## _type(void) \
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{ \
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__asm__ (#_op " " #_type); \
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}
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/* Define function for system instruction with register parameter */
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#define DEFINE_SYSOP_TYPE_PARAM_FUNC(_op, _type) \
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static inline void _op ## _type(u_register_t v) \
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{ \
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__asm__ (#_op " " #_type ", %0" : : "r" (v)); \
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}
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void flush_dcache_range(uintptr_t addr, size_t size);
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void clean_dcache_range(uintptr_t addr, size_t size);
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void inv_dcache_range(uintptr_t addr, size_t size);
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void dcsw_op_louis(u_register_t op_type);
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void dcsw_op_all(u_register_t op_type);
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void disable_mmu_secure(void);
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void disable_mmu_icache_secure(void);
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DEFINE_SYSOP_FUNC(wfi)
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DEFINE_SYSOP_FUNC(wfe)
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DEFINE_SYSOP_FUNC(sev)
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DEFINE_SYSOP_TYPE_FUNC(dsb, sy)
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DEFINE_SYSOP_TYPE_FUNC(dmb, sy)
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DEFINE_SYSOP_TYPE_FUNC(dmb, st)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ld)
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DEFINE_SYSOP_TYPE_FUNC(dsb, ish)
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DEFINE_SYSOP_TYPE_FUNC(dsb, ishst)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ish)
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DEFINE_SYSOP_TYPE_FUNC(dmb, ishst)
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DEFINE_SYSOP_FUNC(isb)
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void __dead2 smc(uint32_t r0, uint32_t r1, uint32_t r2, uint32_t r3,
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uint32_t r4, uint32_t r5, uint32_t r6, uint32_t r7);
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DEFINE_SYSREG_RW_FUNCS(spsr)
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DEFINE_SYSREG_RW_FUNCS(cpsr)
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/*******************************************************************************
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* System register accessor prototypes
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******************************************************************************/
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DEFINE_COPROCR_READ_FUNC(mpidr, MPIDR)
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DEFINE_COPROCR_READ_FUNC(midr, MIDR)
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DEFINE_COPROCR_READ_FUNC(id_pfr1, ID_PFR1)
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DEFINE_COPROCR_READ_FUNC(isr, ISR)
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DEFINE_COPROCR_READ_FUNC(clidr, CLIDR)
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DEFINE_COPROCR_READ_FUNC_64(cntpct, CNTPCT_64)
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DEFINE_COPROCR_RW_FUNCS(scr, SCR)
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DEFINE_COPROCR_RW_FUNCS(ctr, CTR)
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DEFINE_COPROCR_RW_FUNCS(sctlr, SCTLR)
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DEFINE_COPROCR_RW_FUNCS(hsctlr, HSCTLR)
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DEFINE_COPROCR_RW_FUNCS(hcr, HCR)
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DEFINE_COPROCR_RW_FUNCS(hcptr, HCPTR)
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DEFINE_COPROCR_RW_FUNCS(cntfrq, CNTFRQ)
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DEFINE_COPROCR_RW_FUNCS(cnthctl, CNTHCTL)
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DEFINE_COPROCR_RW_FUNCS(mair0, MAIR0)
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DEFINE_COPROCR_RW_FUNCS(mair1, MAIR1)
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DEFINE_COPROCR_RW_FUNCS(ttbcr, TTBCR)
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DEFINE_COPROCR_RW_FUNCS(ttbr0, TTBR0)
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DEFINE_COPROCR_RW_FUNCS_64(ttbr0, TTBR0_64)
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DEFINE_COPROCR_RW_FUNCS(ttbr1, TTBR1)
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DEFINE_COPROCR_RW_FUNCS(vpidr, VPIDR)
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DEFINE_COPROCR_RW_FUNCS(vmpidr, VMPIDR)
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DEFINE_COPROCR_RW_FUNCS_64(vttbr, VTTBR_64)
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DEFINE_COPROCR_RW_FUNCS_64(ttbr1, TTBR1_64)
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DEFINE_COPROCR_RW_FUNCS_64(cntvoff, CNTVOFF_64)
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DEFINE_COPROCR_RW_FUNCS(csselr, CSSELR)
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DEFINE_COPROCR_RW_FUNCS(hstr, HSTR)
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DEFINE_COPROCR_RW_FUNCS(icc_sre_el1, ICC_SRE)
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DEFINE_COPROCR_RW_FUNCS(icc_sre_el2, ICC_HSRE)
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DEFINE_COPROCR_RW_FUNCS(icc_sre_el3, ICC_MSRE)
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DEFINE_COPROCR_RW_FUNCS(icc_pmr_el1, ICC_PMR)
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DEFINE_COPROCR_RW_FUNCS(icc_rpr_el1, ICC_RPR)
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DEFINE_COPROCR_RW_FUNCS(icc_igrpen1_el3, ICC_MGRPEN1)
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DEFINE_COPROCR_RW_FUNCS(icc_igrpen0_el1, ICC_IGRPEN0)
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DEFINE_COPROCR_RW_FUNCS(icc_hppir0_el1, ICC_HPPIR0)
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DEFINE_COPROCR_RW_FUNCS(icc_hppir1_el1, ICC_HPPIR1)
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DEFINE_COPROCR_RW_FUNCS(icc_iar0_el1, ICC_IAR0)
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DEFINE_COPROCR_RW_FUNCS(icc_iar1_el1, ICC_IAR1)
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DEFINE_COPROCR_RW_FUNCS(icc_eoir0_el1, ICC_EOIR0)
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DEFINE_COPROCR_RW_FUNCS(icc_eoir1_el1, ICC_EOIR1)
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DEFINE_COPROCR_RW_FUNCS_64(icc_sgi0r_el1, ICC_SGI0R_EL1_64)
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DEFINE_COPROCR_RW_FUNCS(hdcr, HDCR)
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DEFINE_COPROCR_RW_FUNCS(cnthp_ctl, CNTHP_CTL)
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DEFINE_COPROCR_READ_FUNC(pmcr, PMCR)
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/*
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* TLBI operation prototypes
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*/
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DEFINE_TLBIOP_FUNC(all, TLBIALL)
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DEFINE_TLBIOP_FUNC(allis, TLBIALLIS)
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DEFINE_TLBIOP_PARAM_FUNC(mva, TLBIMVA)
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DEFINE_TLBIOP_PARAM_FUNC(mvaa, TLBIMVAA)
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DEFINE_TLBIOP_PARAM_FUNC(mvaais, TLBIMVAAIS)
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/*
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* BPI operation prototypes.
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*/
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DEFINE_BPIOP_FUNC(allis, BPIALLIS)
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/*
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* DC operation prototypes
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*/
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DEFINE_DCOP_PARAM_FUNC(civac, DCCIMVAC)
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DEFINE_DCOP_PARAM_FUNC(ivac, DCIMVAC)
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DEFINE_DCOP_PARAM_FUNC(cvac, DCCMVAC)
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/* Previously defined accessor functions with incomplete register names */
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#define dsb() dsbsy()
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#define IS_IN_SECURE() \
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(GET_NS_BIT(read_scr()) == 0)
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/*
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* If EL3 is AArch32, then secure PL1 and monitor mode correspond to EL3
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*/
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#define IS_IN_EL3() \
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((GET_M32(read_cpsr()) == MODE32_mon) || \
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(IS_IN_SECURE() && (GET_M32(read_cpsr()) != MODE32_usr)))
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/* Macros for compatibility with AArch64 system registers */
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#define read_mpidr_el1() read_mpidr()
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#define read_scr_el3() read_scr()
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#define write_scr_el3(_v) write_scr(_v)
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#define read_hcr_el2() read_hcr()
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#define write_hcr_el2(_v) write_hcr(_v)
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#define read_cpacr_el1() read_cpacr()
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#define write_cpacr_el1(_v) write_cpacr(_v)
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#define read_cntfrq_el0() read_cntfrq()
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#define write_cntfrq_el0(_v) write_cntfrq(_v)
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#define read_isr_el1() read_isr()
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#define read_cntpct_el0() read64_cntpct()
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#define read_ctr_el0() read_ctr()
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#define write_icc_sgi0r_el1(_v) \
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write64_icc_sgi0r_el1(_v)
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#endif /* __ARCH_HELPERS_H__ */
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