mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-25 22:35:42 +00:00
516 lines
15 KiB
C
516 lines
15 KiB
C
/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __ARCH_H__
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#define __ARCH_H__
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#include <utils_def.h>
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/*******************************************************************************
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* MIDR bit definitions
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******************************************************************************/
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#define MIDR_IMPL_MASK 0xff
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#define MIDR_IMPL_SHIFT 24
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#define MIDR_VAR_SHIFT 20
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#define MIDR_VAR_BITS 4
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#define MIDR_REV_SHIFT 0
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#define MIDR_REV_BITS 4
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#define MIDR_PN_MASK 0xfff
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#define MIDR_PN_SHIFT 4
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/*******************************************************************************
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* MPIDR macros
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******************************************************************************/
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#define MPIDR_MT_MASK (1 << 24)
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#define MPIDR_CPU_MASK MPIDR_AFFLVL_MASK
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#define MPIDR_CLUSTER_MASK (MPIDR_AFFLVL_MASK << MPIDR_AFFINITY_BITS)
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#define MPIDR_AFFINITY_BITS 8
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#define MPIDR_AFFLVL_MASK 0xff
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#define MPIDR_AFFLVL_SHIFT 3
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#define MPIDR_AFF0_SHIFT 0
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#define MPIDR_AFF1_SHIFT 8
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#define MPIDR_AFF2_SHIFT 16
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#define MPIDR_AFFINITY_MASK 0x00ffffff
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#define MPIDR_AFFLVL0 0
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#define MPIDR_AFFLVL1 1
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#define MPIDR_AFFLVL2 2
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#define MPIDR_AFFLVL0_VAL(mpidr) \
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(((mpidr) >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL1_VAL(mpidr) \
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(((mpidr) >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL2_VAL(mpidr) \
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(((mpidr) >> MPIDR_AFF2_SHIFT) & MPIDR_AFFLVL_MASK)
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#define MPIDR_AFFLVL3_VAL(mpidr) 0
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/*
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* The MPIDR_MAX_AFFLVL count starts from 0. Take care to
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* add one while using this macro to define array sizes.
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*/
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#define MPIDR_MAX_AFFLVL 2
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/* Data Cache set/way op type defines */
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#define DC_OP_ISW 0x0
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#define DC_OP_CISW 0x1
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#define DC_OP_CSW 0x2
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/*******************************************************************************
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* Generic timer memory mapped registers & offsets
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******************************************************************************/
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#define CNTCR_OFF 0x000
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#define CNTFID_OFF 0x020
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#define CNTCR_EN (1 << 0)
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#define CNTCR_HDBG (1 << 1)
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#define CNTCR_FCREQ(x) ((x) << 8)
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/*******************************************************************************
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* System register bit definitions
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******************************************************************************/
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/* CLIDR definitions */
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#define LOUIS_SHIFT 21
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#define LOC_SHIFT 24
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#define CLIDR_FIELD_WIDTH 3
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/* CSSELR definitions */
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#define LEVEL_SHIFT 1
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/* ID_PFR1 definitions */
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#define ID_PFR1_VIRTEXT_SHIFT 12
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#define ID_PFR1_VIRTEXT_MASK 0xf
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#define GET_VIRT_EXT(id) (((id) >> ID_PFR1_VIRTEXT_SHIFT) \
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& ID_PFR1_VIRTEXT_MASK)
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#define ID_PFR1_GIC_SHIFT 28
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#define ID_PFR1_GIC_MASK 0xf
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/* SCTLR definitions */
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#define SCTLR_RES1 ((1 << 23) | (1 << 22) | (1 << 11) | (1 << 4) | \
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(1 << 3))
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#define SCTLR_M_BIT (1 << 0)
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#define SCTLR_A_BIT (1 << 1)
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#define SCTLR_C_BIT (1 << 2)
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#define SCTLR_CP15BEN_BIT (1 << 5)
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#define SCTLR_ITD_BIT (1 << 7)
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#define SCTLR_I_BIT (1 << 12)
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#define SCTLR_V_BIT (1 << 13)
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#define SCTLR_NTWI_BIT (1 << 16)
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#define SCTLR_NTWE_BIT (1 << 18)
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#define SCTLR_WXN_BIT (1 << 19)
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#define SCTLR_UWXN_BIT (1 << 20)
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#define SCTLR_EE_BIT (1 << 25)
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#define SCTLR_TRE_BIT (1 << 28)
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#define SCTLR_AFE_BIT (1 << 29)
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#define SCTLR_TE_BIT (1 << 30)
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#define SCTLR_RESET_VAL (SCTLR_RES1 | SCTLR_NTWE_BIT | \
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SCTLR_NTWI_BIT | SCTLR_CP15BEN_BIT)
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/* SDCR definitions */
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#define SDCR_SPD(x) ((x) << 14)
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#define SDCR_SPD_LEGACY 0x0
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#define SDCR_SPD_DISABLE 0x2
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#define SDCR_SPD_ENABLE 0x3
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#define SDCR_RESET_VAL 0x0
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#if !ERROR_DEPRECATED
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#define SDCR_DEF_VAL SDCR_SPD(SDCR_SPD_DISABLE)
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#endif
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/* HSCTLR definitions */
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#define HSCTLR_RES1 ((1 << 29) | (1 << 28) | (1 << 23) | (1 << 22) \
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| (1 << 18) | (1 << 16) | (1 << 11) | (1 << 4) \
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| (1 << 3))
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#define HSCTLR_M_BIT (1 << 0)
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#define HSCTLR_A_BIT (1 << 1)
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#define HSCTLR_C_BIT (1 << 2)
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#define HSCTLR_CP15BEN_BIT (1 << 5)
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#define HSCTLR_ITD_BIT (1 << 7)
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#define HSCTLR_SED_BIT (1 << 8)
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#define HSCTLR_I_BIT (1 << 12)
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#define HSCTLR_WXN_BIT (1 << 19)
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#define HSCTLR_EE_BIT (1 << 25)
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#define HSCTLR_TE_BIT (1 << 30)
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/* CPACR definitions */
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#define CPACR_FPEN(x) ((x) << 20)
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#define CPACR_FP_TRAP_PL0 0x1
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#define CPACR_FP_TRAP_ALL 0x2
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#define CPACR_FP_TRAP_NONE 0x3
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/* SCR definitions */
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#define SCR_TWE_BIT (1 << 13)
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#define SCR_TWI_BIT (1 << 12)
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#define SCR_SIF_BIT (1 << 9)
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#define SCR_HCE_BIT (1 << 8)
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#define SCR_SCD_BIT (1 << 7)
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#define SCR_NET_BIT (1 << 6)
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#define SCR_AW_BIT (1 << 5)
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#define SCR_FW_BIT (1 << 4)
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#define SCR_EA_BIT (1 << 3)
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#define SCR_FIQ_BIT (1 << 2)
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#define SCR_IRQ_BIT (1 << 1)
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#define SCR_NS_BIT (1 << 0)
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#define SCR_VALID_BIT_MASK 0x33ff
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#define SCR_RESET_VAL 0x0
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#define GET_NS_BIT(scr) ((scr) & SCR_NS_BIT)
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/* HCR definitions */
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#define HCR_AMO_BIT (1 << 5)
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#define HCR_IMO_BIT (1 << 4)
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#define HCR_FMO_BIT (1 << 3)
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#define HCR_RESET_VAL 0x0
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/* CNTHCTL definitions */
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#define CNTHCTL_RESET_VAL 0x0
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#define PL1PCEN_BIT (1 << 1)
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#define PL1PCTEN_BIT (1 << 0)
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/* CNTKCTL definitions */
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#define PL0PTEN_BIT (1 << 9)
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#define PL0VTEN_BIT (1 << 8)
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#define PL0PCTEN_BIT (1 << 0)
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#define PL0VCTEN_BIT (1 << 1)
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#define EVNTEN_BIT (1 << 2)
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#define EVNTDIR_BIT (1 << 3)
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#define EVNTI_SHIFT 4
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#define EVNTI_MASK 0xf
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/* HCPTR definitions */
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#define HCPTR_RES1 ((1 << 13) | (1<<12) | 0x3ff)
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#define TCPAC_BIT (1 << 31)
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#define TTA_BIT (1 << 20)
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#define TCP11_BIT (1 << 10)
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#define TCP10_BIT (1 << 10)
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#define HCPTR_RESET_VAL HCPTR_RES1
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/* VTTBR defintions */
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#define VTTBR_RESET_VAL ULL(0x0)
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#define VTTBR_VMID_MASK ULL(0xff)
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#define VTTBR_VMID_SHIFT 48
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#define VTTBR_BADDR_MASK 0xffffffffffff
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#define VTTBR_BADDR_SHIFT 0
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/* HDCR definitions */
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#define HDCR_RESET_VAL 0x0
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/* HSTR definitions */
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#define HSTR_RESET_VAL 0x0
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/* CNTHP_CTL definitions */
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#define CNTHP_CTL_RESET_VAL 0x0
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/* NASCR definitions */
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#define NSASEDIS_BIT (1 << 15)
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#define NSTRCDIS_BIT (1 << 20)
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/* NOTE: correct typo in the definitions */
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#if !ERROR_DEPRECATED
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#define NASCR_CP11_BIT (1 << 11)
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#define NASCR_CP10_BIT (1 << 10)
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#endif
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#define NSACR_CP11_BIT (1 << 11)
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#define NSACR_CP10_BIT (1 << 10)
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#define NSACR_IMP_DEF_MASK (0x7 << 16)
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#define NSACR_ENABLE_FP_ACCESS (NSACR_CP11_BIT | NSACR_CP10_BIT)
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#define NSACR_RESET_VAL 0x0
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/* CPACR definitions */
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#define ASEDIS_BIT (1 << 31)
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#define TRCDIS_BIT (1 << 28)
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#define CPACR_CP11_SHIFT 22
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#define CPACR_CP10_SHIFT 20
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#define CPACR_ENABLE_FP_ACCESS (0x3 << CPACR_CP11_SHIFT |\
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0x3 << CPACR_CP10_SHIFT)
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#define CPACR_RESET_VAL 0x0
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/* FPEXC definitions */
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#define FPEXC_RES1 ((1 << 10) | (1 << 9) | (1 << 8))
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#define FPEXC_EN_BIT (1 << 30)
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#define FPEXC_RESET_VAL FPEXC_RES1
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/* SPSR/CPSR definitions */
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#define SPSR_FIQ_BIT (1 << 0)
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#define SPSR_IRQ_BIT (1 << 1)
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#define SPSR_ABT_BIT (1 << 2)
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#define SPSR_AIF_SHIFT 6
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#define SPSR_AIF_MASK 0x7
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#define SPSR_E_SHIFT 9
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#define SPSR_E_MASK 0x1
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#define SPSR_E_LITTLE 0
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#define SPSR_E_BIG 1
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#define SPSR_T_SHIFT 5
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#define SPSR_T_MASK 0x1
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#define SPSR_T_ARM 0
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#define SPSR_T_THUMB 1
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#define SPSR_MODE_SHIFT 0
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#define SPSR_MODE_MASK 0x7
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#define DISABLE_ALL_EXCEPTIONS \
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(SPSR_FIQ_BIT | SPSR_IRQ_BIT | SPSR_ABT_BIT)
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/*
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* TTBCR definitions
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*/
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/* The ARM Trusted Firmware uses the long descriptor format */
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#define TTBCR_EAE_BIT (1 << 31)
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#define TTBCR_SH1_NON_SHAREABLE (0x0 << 28)
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#define TTBCR_SH1_OUTER_SHAREABLE (0x2 << 28)
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#define TTBCR_SH1_INNER_SHAREABLE (0x3 << 28)
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#define TTBCR_RGN1_OUTER_NC (0x0 << 26)
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#define TTBCR_RGN1_OUTER_WBA (0x1 << 26)
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#define TTBCR_RGN1_OUTER_WT (0x2 << 26)
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#define TTBCR_RGN1_OUTER_WBNA (0x3 << 26)
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#define TTBCR_RGN1_INNER_NC (0x0 << 24)
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#define TTBCR_RGN1_INNER_WBA (0x1 << 24)
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#define TTBCR_RGN1_INNER_WT (0x2 << 24)
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#define TTBCR_RGN1_INNER_WBNA (0x3 << 24)
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#define TTBCR_EPD1_BIT (1 << 23)
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#define TTBCR_A1_BIT (1 << 22)
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#define TTBCR_T1SZ_SHIFT 16
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#define TTBCR_T1SZ_MASK (0x7)
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#define TTBCR_TxSZ_MIN 0
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#define TTBCR_TxSZ_MAX 7
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#define TTBCR_SH0_NON_SHAREABLE (0x0 << 12)
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#define TTBCR_SH0_OUTER_SHAREABLE (0x2 << 12)
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#define TTBCR_SH0_INNER_SHAREABLE (0x3 << 12)
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#define TTBCR_RGN0_OUTER_NC (0x0 << 10)
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#define TTBCR_RGN0_OUTER_WBA (0x1 << 10)
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#define TTBCR_RGN0_OUTER_WT (0x2 << 10)
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#define TTBCR_RGN0_OUTER_WBNA (0x3 << 10)
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#define TTBCR_RGN0_INNER_NC (0x0 << 8)
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#define TTBCR_RGN0_INNER_WBA (0x1 << 8)
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#define TTBCR_RGN0_INNER_WT (0x2 << 8)
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#define TTBCR_RGN0_INNER_WBNA (0x3 << 8)
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#define TTBCR_EPD0_BIT (1 << 7)
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#define TTBCR_T0SZ_SHIFT 0
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#define TTBCR_T0SZ_MASK (0x7)
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#define MODE_RW_SHIFT 0x4
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#define MODE_RW_MASK 0x1
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#define MODE_RW_32 0x1
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#define MODE32_SHIFT 0
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#define MODE32_MASK 0x1f
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#define MODE32_usr 0x10
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#define MODE32_fiq 0x11
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#define MODE32_irq 0x12
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#define MODE32_svc 0x13
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#define MODE32_mon 0x16
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#define MODE32_abt 0x17
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#define MODE32_hyp 0x1a
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#define MODE32_und 0x1b
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#define MODE32_sys 0x1f
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#define GET_M32(mode) (((mode) >> MODE32_SHIFT) & MODE32_MASK)
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#define SPSR_MODE32(mode, isa, endian, aif) \
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(MODE_RW_32 << MODE_RW_SHIFT | \
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((mode) & MODE32_MASK) << MODE32_SHIFT | \
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((isa) & SPSR_T_MASK) << SPSR_T_SHIFT | \
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((endian) & SPSR_E_MASK) << SPSR_E_SHIFT | \
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((aif) & SPSR_AIF_MASK) << SPSR_AIF_SHIFT)
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/*
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* TTBR definitions
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*/
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#define TTBR_CNP_BIT 0x1
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/*
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* CTR definitions
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*/
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#define CTR_CWG_SHIFT 24
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#define CTR_CWG_MASK 0xf
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#define CTR_ERG_SHIFT 20
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#define CTR_ERG_MASK 0xf
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#define CTR_DMINLINE_SHIFT 16
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#define CTR_DMINLINE_WIDTH 4
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#define CTR_DMINLINE_MASK ((1 << 4) - 1)
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#define CTR_L1IP_SHIFT 14
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#define CTR_L1IP_MASK 0x3
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#define CTR_IMINLINE_SHIFT 0
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#define CTR_IMINLINE_MASK 0xf
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#define MAX_CACHE_LINE_SIZE 0x800 /* 2KB */
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/* PMCR definitions */
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#define PMCR_N_SHIFT 11
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#define PMCR_N_MASK 0x1f
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#define PMCR_N_BITS (PMCR_N_MASK << PMCR_N_SHIFT)
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#define PMCR_LC_BIT (1 << 6)
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#define PMCR_DP_BIT (1 << 5)
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/*******************************************************************************
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* Definitions of register offsets, fields and macros for CPU system
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* instructions.
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******************************************************************************/
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#define TLBI_ADDR_SHIFT 0
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#define TLBI_ADDR_MASK 0xFFFFF000
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#define TLBI_ADDR(x) (((x) >> TLBI_ADDR_SHIFT) & TLBI_ADDR_MASK)
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/*******************************************************************************
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* Definitions of register offsets and fields in the CNTCTLBase Frame of the
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* system level implementation of the Generic Timer.
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******************************************************************************/
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#define CNTNSAR 0x4
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#define CNTNSAR_NS_SHIFT(x) (x)
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#define CNTACR_BASE(x) (0x40 + ((x) << 2))
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#define CNTACR_RPCT_SHIFT 0x0
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#define CNTACR_RVCT_SHIFT 0x1
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#define CNTACR_RFRQ_SHIFT 0x2
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#define CNTACR_RVOFF_SHIFT 0x3
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#define CNTACR_RWVT_SHIFT 0x4
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#define CNTACR_RWPT_SHIFT 0x5
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/* MAIR macros */
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#define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << 3))
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#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - 3) << 3))
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/* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */
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#define SCR p15, 0, c1, c1, 0
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#define SCTLR p15, 0, c1, c0, 0
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#define SDCR p15, 0, c1, c3, 1
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#define MPIDR p15, 0, c0, c0, 5
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#define MIDR p15, 0, c0, c0, 0
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#define VBAR p15, 0, c12, c0, 0
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#define MVBAR p15, 0, c12, c0, 1
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#define NSACR p15, 0, c1, c1, 2
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#define CPACR p15, 0, c1, c0, 2
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#define DCCIMVAC p15, 0, c7, c14, 1
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#define DCCMVAC p15, 0, c7, c10, 1
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#define DCIMVAC p15, 0, c7, c6, 1
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#define DCCISW p15, 0, c7, c14, 2
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#define DCCSW p15, 0, c7, c10, 2
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#define DCISW p15, 0, c7, c6, 2
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#define CTR p15, 0, c0, c0, 1
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#define CNTFRQ p15, 0, c14, c0, 0
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#define ID_PFR1 p15, 0, c0, c1, 1
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#define MAIR0 p15, 0, c10, c2, 0
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#define MAIR1 p15, 0, c10, c2, 1
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#define TTBCR p15, 0, c2, c0, 2
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#define TTBR0 p15, 0, c2, c0, 0
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#define TTBR1 p15, 0, c2, c0, 1
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#define TLBIALL p15, 0, c8, c7, 0
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#define TLBIALLIS p15, 0, c8, c3, 0
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#define TLBIMVA p15, 0, c8, c7, 1
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#define TLBIMVAA p15, 0, c8, c7, 3
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#define TLBIMVAAIS p15, 0, c8, c3, 3
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#define BPIALLIS p15, 0, c7, c1, 6
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#define HSCTLR p15, 4, c1, c0, 0
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#define HCR p15, 4, c1, c1, 0
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#define HCPTR p15, 4, c1, c1, 2
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#define HSTR p15, 4, c1, c1, 3
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#define CNTHCTL p15, 4, c14, c1, 0
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#define CNTKCTL p15, 0, c14, c1, 0
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#define VPIDR p15, 4, c0, c0, 0
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#define VMPIDR p15, 4, c0, c0, 5
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#define ISR p15, 0, c12, c1, 0
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#define CLIDR p15, 1, c0, c0, 1
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#define CSSELR p15, 2, c0, c0, 0
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#define CCSIDR p15, 1, c0, c0, 0
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#define DBGOSDLR p14, 0, c1, c3, 4
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/* Debug register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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#define HDCR p15, 4, c1, c1, 1
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#define PMCR p15, 0, c9, c12, 0
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#define CNTHP_CTL p15, 4, c14, c2, 1
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/* GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRn, CRm, opt2 */
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#define ICC_IAR1 p15, 0, c12, c12, 0
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#define ICC_IAR0 p15, 0, c12, c8, 0
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#define ICC_EOIR1 p15, 0, c12, c12, 1
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#define ICC_EOIR0 p15, 0, c12, c8, 1
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#define ICC_HPPIR1 p15, 0, c12, c12, 2
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#define ICC_HPPIR0 p15, 0, c12, c8, 2
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#define ICC_BPR1 p15, 0, c12, c12, 3
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#define ICC_BPR0 p15, 0, c12, c8, 3
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#define ICC_DIR p15, 0, c12, c11, 1
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#define ICC_PMR p15, 0, c4, c6, 0
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#define ICC_RPR p15, 0, c12, c11, 3
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#define ICC_CTLR p15, 0, c12, c12, 4
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#define ICC_MCTLR p15, 6, c12, c12, 4
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#define ICC_SRE p15, 0, c12, c12, 5
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#define ICC_HSRE p15, 4, c12, c9, 5
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#define ICC_MSRE p15, 6, c12, c12, 5
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#define ICC_IGRPEN0 p15, 0, c12, c12, 6
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#define ICC_IGRPEN1 p15, 0, c12, c12, 7
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#define ICC_MGRPEN1 p15, 6, c12, c12, 7
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/* 64 bit system register defines The format is: coproc, opt1, CRm */
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#define TTBR0_64 p15, 0, c2
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#define TTBR1_64 p15, 1, c2
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#define CNTVOFF_64 p15, 4, c14
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#define VTTBR_64 p15, 6, c2
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#define CNTPCT_64 p15, 0, c14
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/* 64 bit GICv3 CPU Interface system register defines. The format is: coproc, opt1, CRm */
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#define ICC_SGI1R_EL1_64 p15, 0, c12
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#define ICC_ASGI1R_EL1_64 p15, 1, c12
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#define ICC_SGI0R_EL1_64 p15, 2, c12
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/*******************************************************************************
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* Definitions of MAIR encodings for device and normal memory
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******************************************************************************/
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/*
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* MAIR encodings for device memory attributes.
|
|
*/
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#define MAIR_DEV_nGnRnE U(0x0)
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#define MAIR_DEV_nGnRE U(0x4)
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#define MAIR_DEV_nGRE U(0x8)
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#define MAIR_DEV_GRE U(0xc)
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|
|
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/*
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* MAIR encodings for normal memory attributes.
|
|
*
|
|
* Cache Policy
|
|
* WT: Write Through
|
|
* WB: Write Back
|
|
* NC: Non-Cacheable
|
|
*
|
|
* Transient Hint
|
|
* NTR: Non-Transient
|
|
* TR: Transient
|
|
*
|
|
* Allocation Policy
|
|
* RA: Read Allocate
|
|
* WA: Write Allocate
|
|
* RWA: Read and Write Allocate
|
|
* NA: No Allocation
|
|
*/
|
|
#define MAIR_NORM_WT_TR_WA U(0x1)
|
|
#define MAIR_NORM_WT_TR_RA U(0x2)
|
|
#define MAIR_NORM_WT_TR_RWA U(0x3)
|
|
#define MAIR_NORM_NC U(0x4)
|
|
#define MAIR_NORM_WB_TR_WA U(0x5)
|
|
#define MAIR_NORM_WB_TR_RA U(0x6)
|
|
#define MAIR_NORM_WB_TR_RWA U(0x7)
|
|
#define MAIR_NORM_WT_NTR_NA U(0x8)
|
|
#define MAIR_NORM_WT_NTR_WA U(0x9)
|
|
#define MAIR_NORM_WT_NTR_RA U(0xa)
|
|
#define MAIR_NORM_WT_NTR_RWA U(0xb)
|
|
#define MAIR_NORM_WB_NTR_NA U(0xc)
|
|
#define MAIR_NORM_WB_NTR_WA U(0xd)
|
|
#define MAIR_NORM_WB_NTR_RA U(0xe)
|
|
#define MAIR_NORM_WB_NTR_RWA U(0xf)
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|
|
|
#define MAIR_NORM_OUTER_SHIFT 4
|
|
|
|
#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
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|
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#endif /* __ARCH_H__ */
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