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62320dc4fd
TC3 is a little different from TC2: * new address for its second DRAM bank * new CPUs * a few interrupts have changed * new SCP MHU base address. * utility space address (needed for MPAM) is different * no CMN (and therefore cmn-pmu) * the uart clock is different This requires the dts to be different between revisions for the first time. Introduce a tc_vers.dtsi that includes only definitions for things that are different. Signed-off-by: Tintu Thomas <tintu.thomas@arm.com> Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I2940d87a69ea93502b7f5a22a539e4b70a63e827
32 lines
927 B
Text
32 lines
927 B
Text
/*
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* Copyright (c) 2023-2024, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#if TARGET_PLATFORM <= 2
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#define INT_MBOX_RX 317
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#define MHU_TX_ADDR(pref) pref##45000000 /* hex */
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#define MHU_RX_ADDR(pref) pref##45010000 /* hex */
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#define MPAM_ADDR 0x1 0x00010000 /* 0x1_0001_0000 */
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#define UARTCLK_FREQ 5000000
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#elif TARGET_PLATFORM == 3
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#define INT_MBOX_RX 300
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#define MHU_TX_ADDR(pref) pref##46040000 /* hex */
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#define MHU_RX_ADDR(pref) pref##46140000 /* hex */
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#define MPAM_ADDR 0x0 0x5f010000 /* 0x5f01_0000 */
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#define UARTCLK_FREQ 3750000
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#endif /* TARGET_PLATFORM == 3 */
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/ {
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#if TARGET_PLATFORM <= 2
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cmn-pmu {
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compatible = "arm,ci-700";
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reg = <0x0 0x50000000 0x0 0x10000000>;
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interrupts = <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>;
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};
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#endif /* TARGET_PLATFORM <= 2 */
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};
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