mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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61b5ef21af
Initializing all early clocks before the MMU is enabled can impact boot time. Therefore, splitting the setup into A53 clocks and peripheral clocks can be beneficial, with the peripheral clocks configured after fully initializing the MMU. Change-Id: I19644227b66effab8e2c43e64e057ea0c8625ebc Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
138 lines
2.9 KiB
C
138 lines
2.9 KiB
C
/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <common/debug.h>
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#include <common/desc_image_load.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <plat_console.h>
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#include <s32cc-clk-drv.h>
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#include <plat_io_storage.h>
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#include <s32cc-bl-common.h>
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#include <s32cc-ncore.h>
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#define SIUL20_BASE UL(0x4009C000)
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#define SIUL2_PC09_MSCR UL(0x4009C2E4)
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#define SIUL2_PC10_MSCR UL(0x4009C2E8)
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#define SIUL2_PC10_LIN0_IMCR UL(0x4009CA40)
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#define LIN0_TX_MSCR_CFG U(0x00214001)
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#define LIN0_RX_MSCR_CFG U(0x00094000)
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#define LIN0_RX_IMCR_CFG U(0x00000002)
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struct bl_load_info *plat_get_bl_image_load_info(void)
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{
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return get_bl_load_info_from_mem_params_desc();
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}
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struct bl_params *plat_get_next_bl_params(void)
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{
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return get_next_bl_params_from_mem_params_desc();
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}
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void plat_flush_next_bl_params(void)
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{
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flush_bl_params_desc();
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}
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void bl2_platform_setup(void)
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{
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int ret;
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ret = mmap_add_dynamic_region(S32G_FIP_BASE, S32G_FIP_BASE,
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S32G_FIP_SIZE,
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MT_MEMORY | MT_RW | MT_SECURE);
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if (ret != 0) {
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panic();
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}
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}
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static int s32g_mmap_siul2(void)
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{
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return mmap_add_dynamic_region(SIUL20_BASE, SIUL20_BASE, PAGE_SIZE,
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MT_DEVICE | MT_RW | MT_SECURE);
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}
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static void linflex_config_pinctrl(void)
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{
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/* set PC09 - MSCR[41] - for UART0 TXD */
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mmio_write_32(SIUL2_PC09_MSCR, LIN0_TX_MSCR_CFG);
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/* set PC10 - MSCR[42] - for UART0 RXD */
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mmio_write_32(SIUL2_PC10_MSCR, LIN0_RX_MSCR_CFG);
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/* set PC10 - MSCR[512]/IMCR[0] - for UART0 RXD */
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mmio_write_32(SIUL2_PC10_LIN0_IMCR, LIN0_RX_IMCR_CFG);
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}
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void bl2_el3_early_platform_setup(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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int ret;
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/* Restore (clear) the CAIUTC[IsolEn] bit for the primary cluster, which
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* we have manually set during early BL2 boot.
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*/
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ncore_disable_caiu_isolation(A53_CLUSTER0_CAIU);
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ncore_init();
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ncore_caiu_online(A53_CLUSTER0_CAIU);
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ret = s32cc_init_core_clocks();
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if (ret != 0) {
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panic();
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}
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ret = s32cc_bl_mmu_setup();
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if (ret != 0) {
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panic();
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}
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ret = s32cc_init_early_clks();
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if (ret != 0) {
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panic();
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}
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ret = s32g_mmap_siul2();
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if (ret != 0) {
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panic();
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}
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linflex_config_pinctrl();
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console_s32g2_register();
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plat_s32g2_io_setup();
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}
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void bl2_el3_plat_arch_setup(void)
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{
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}
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int bl2_plat_handle_pre_image_load(unsigned int image_id)
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{
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const struct bl_mem_params_node *desc = get_bl_mem_params_node(image_id);
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const struct image_info *img_info;
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size_t size;
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if (desc == NULL) {
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return -EINVAL;
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}
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img_info = &desc->image_info;
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if ((img_info == NULL) || (img_info->image_max_size == 0U)) {
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return -EINVAL;
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}
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size = page_align(img_info->image_max_size, UP);
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return mmap_add_dynamic_region(img_info->image_base,
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img_info->image_base,
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size,
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MT_MEMORY | MT_RW | MT_SECURE);
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}
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