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https://github.com/ARM-software/arm-trusted-firmware.git
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60e8f3cfd5
This patch introduces a build flag which allows the xlat tables to be mapped in a read-only region within BL31 memory. It makes it much harder for someone who has acquired the ability to write to arbitrary secure memory addresses to gain control of the translation tables. The memory attributes of the descriptors describing the tables themselves are changed to read-only secure data. This change happens at the end of BL31 runtime setup. Until this point, the tables have read-write permissions. This gives a window of opportunity for changes to be made to the tables with the MMU on (e.g. reclaiming init code). No changes can be made to the tables with the MMU turned on from this point onwards. This change is also enabled for sp_min and tspd. To make all this possible, the base table was moved to .rodata. The penalty we pay is that now .rodata must be aligned to the size of the base table (512B alignment). Still, this is better than putting the base table with the higher level tables in the xlat_table section, as that would cost us a full 4KB page. Changing the tables from read-write to read-only cannot be done with the MMU on, as the break-before-make sequence would invalidate the descriptor which resolves the level 3 page table where that very descriptor is located. This would make the translation required for writing the changes impossible, generating an MMU fault. The caches are also flushed. Signed-off-by: Petre-Ionut Tudor <petre-ionut.tudor@arm.com> Change-Id: Ibe5de307e6dc94c67d6186139ac3973516430466
86 lines
2.3 KiB
C
86 lines
2.3 KiB
C
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <platform_def.h>
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#include <bl32/tsp/platform_tsp.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <drivers/arm/pl011.h>
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#include <drivers/console.h>
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#include <plat/arm/common/plat_arm.h>
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/* Weak definitions may be overridden in specific ARM standard platform */
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#pragma weak tsp_early_platform_setup
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#pragma weak tsp_platform_setup
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#pragma weak tsp_plat_arch_setup
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#define MAP_BL_TSP_TOTAL MAP_REGION_FLAT( \
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BL32_BASE, \
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BL32_END - BL32_BASE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*******************************************************************************
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* Initialize the UART
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******************************************************************************/
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static console_pl011_t arm_tsp_runtime_console;
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void arm_tsp_early_platform_setup(void)
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{
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/*
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* Initialize a different console than already in use to display
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* messages from TSP
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*/
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int rc = console_pl011_register(PLAT_ARM_TSP_UART_BASE,
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PLAT_ARM_TSP_UART_CLK_IN_HZ,
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ARM_CONSOLE_BAUDRATE,
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&arm_tsp_runtime_console);
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if (rc == 0)
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panic();
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console_set_scope(&arm_tsp_runtime_console.console,
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CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
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}
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void tsp_early_platform_setup(void)
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{
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arm_tsp_early_platform_setup();
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}
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/*******************************************************************************
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* Perform platform specific setup placeholder
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******************************************************************************/
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void tsp_platform_setup(void)
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{
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plat_arm_gic_driver_init();
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}
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only intializes the MMU
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******************************************************************************/
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void tsp_plat_arch_setup(void)
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{
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#if USE_COHERENT_MEM
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/* Ensure ARM platforms don't use coherent memory in TSP */
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assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
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#endif
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const mmap_region_t bl_regions[] = {
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MAP_BL_TSP_TOTAL,
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ARM_MAP_BL_RO,
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{0}
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};
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setup_page_tables(bl_regions, plat_arm_get_mmap());
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enable_mmu_el1(0);
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#if PLAT_RO_XLAT_TABLES
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arm_xlat_make_tables_readonly();
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#endif
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}
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