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https://github.com/ARM-software/arm-trusted-firmware.git
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1083b2b315
Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
158 lines
4.6 KiB
C
158 lines
4.6 KiB
C
/*
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* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef FVP_DEF_H
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#define FVP_DEF_H
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#include <utils_def.h>
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#ifndef FVP_CLUSTER_COUNT
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#define FVP_CLUSTER_COUNT 2
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#endif
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#ifndef FVP_MAX_CPUS_PER_CLUSTER
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#define FVP_MAX_CPUS_PER_CLUSTER 4
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#endif
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#ifndef FVP_MAX_PE_PER_CPU
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# define FVP_MAX_PE_PER_CPU 1
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#endif
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#define FVP_PRIMARY_CPU 0x0
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/* Defines for the Interconnect build selection */
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#define FVP_CCI 1
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#define FVP_CCN 2
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/*******************************************************************************
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* FVP memory map related constants
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******************************************************************************/
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#define FLASH1_BASE 0x0c000000
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#define FLASH1_SIZE 0x04000000
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#define PSRAM_BASE 0x14000000
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#define PSRAM_SIZE 0x04000000
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#define VRAM_BASE 0x18000000
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#define VRAM_SIZE 0x02000000
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/* Aggregate of all devices in the first GB */
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#define DEVICE0_BASE 0x20000000
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#define DEVICE0_SIZE 0x0c200000
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/*
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* In case of FVP models with CCN, the CCN register space overlaps into
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* the NSRAM area.
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*/
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#if FVP_INTERCONNECT_DRIVER == FVP_CCN
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#define DEVICE1_BASE 0x2e000000
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#define DEVICE1_SIZE 0x1A00000
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#else
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#define DEVICE1_BASE 0x2f000000
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#define DEVICE1_SIZE 0x200000
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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#endif
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/* Devices in the second GB */
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#define DEVICE2_BASE 0x7fe00000
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#define DEVICE2_SIZE 0x00200000
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#define PCIE_EXP_BASE 0x40000000
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#define TZRNG_BASE 0x7fe60000
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/* Non-volatile counters */
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#define TRUSTED_NVCTR_BASE 0x7fe70000
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#define TFW_NVCTR_BASE (TRUSTED_NVCTR_BASE + 0x0000)
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#define TFW_NVCTR_SIZE 4
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#define NTFW_CTR_BASE (TRUSTED_NVCTR_BASE + 0x0004)
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#define NTFW_CTR_SIZE 4
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/* Keys */
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#define SOC_KEYS_BASE 0x7fe80000
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#define TZ_PUB_KEY_HASH_BASE (SOC_KEYS_BASE + 0x0000)
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#define TZ_PUB_KEY_HASH_SIZE 32
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#define HU_KEY_BASE (SOC_KEYS_BASE + 0x0020)
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#define HU_KEY_SIZE 16
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#define END_KEY_BASE (SOC_KEYS_BASE + 0x0044)
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#define END_KEY_SIZE 32
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/* Constants to distinguish FVP type */
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#define HBI_BASE_FVP 0x020
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#define REV_BASE_FVP_V0 0x0
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#define REV_BASE_FVP_REVC 0x2
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#define HBI_FOUNDATION_FVP 0x010
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#define REV_FOUNDATION_FVP_V2_0 0x0
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#define REV_FOUNDATION_FVP_V2_1 0x1
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#define REV_FOUNDATION_FVP_v9_1 0x2
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#define REV_FOUNDATION_FVP_v9_6 0x3
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#define BLD_GIC_VE_MMAP 0x0
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#define BLD_GIC_A53A57_MMAP 0x1
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#define ARCH_MODEL 0x1
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/* FVP Power controller base address*/
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#define PWRC_BASE 0x1c100000
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/* FVP SP804 timer frequency is 35 MHz*/
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#define SP804_TIMER_CLKMULT 1
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#define SP804_TIMER_CLKDIV 35
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/* SP810 controller. FVP specific flags */
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#define FVP_SP810_CTRL_TIM0_OV (1 << 16)
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#define FVP_SP810_CTRL_TIM1_OV (1 << 18)
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#define FVP_SP810_CTRL_TIM2_OV (1 << 20)
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#define FVP_SP810_CTRL_TIM3_OV (1 << 22)
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/*******************************************************************************
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* GIC-400 & interrupt handling related constants
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******************************************************************************/
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/* VE compatible GIC memory map */
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#define VE_GICD_BASE 0x2c001000
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#define VE_GICC_BASE 0x2c002000
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#define VE_GICH_BASE 0x2c004000
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#define VE_GICV_BASE 0x2c006000
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/* Base FVP compatible GIC memory map */
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#define BASE_GICD_BASE 0x2f000000
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#define BASE_GICR_BASE 0x2f100000
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#define BASE_GICC_BASE 0x2c000000
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#define BASE_GICH_BASE 0x2c010000
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#define BASE_GICV_BASE 0x2c02f000
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#define FVP_IRQ_TZ_WDOG 56
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#define FVP_IRQ_SEC_SYS_TIMER 57
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/*******************************************************************************
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* TrustZone address space controller related constants
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******************************************************************************/
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/* NSAIDs used by devices in TZC filter 0 on FVP */
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#define FVP_NSAID_DEFAULT 0
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#define FVP_NSAID_PCI 1
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#define FVP_NSAID_VIRTIO 8 /* from FVP v5.6 onwards */
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#define FVP_NSAID_AP 9 /* Application Processors */
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#define FVP_NSAID_VIRTIO_OLD 15 /* until FVP v5.5 */
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/* NSAIDs used by devices in TZC filter 2 on FVP */
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#define FVP_NSAID_HDLCD0 2
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#define FVP_NSAID_CLCD 7
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/*******************************************************************************
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* Memprotect definitions
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******************************************************************************/
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/* PSCI memory protect definitions:
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* This variable is stored in a non-secure flash because some ARM reference
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* platforms do not have secure NVRAM. Real systems that provided MEM_PROTECT
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* support must use a secure NVRAM to store the PSCI MEM_PROTECT definitions.
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*/
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#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
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V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
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#endif /* FVP_DEF_H */
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