mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 17:44:19 +00:00
60d330dc4d
Combining the EL2 and EL3 enablement code necessitates that it must be called at el3_exit, which is the only place with enough context to make the decision of what needs to be set. Decouple them to allow them to be called from elsewhere. Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I147764c42771e7d4100699ec8fae98dac0a505c0
63 lines
1.7 KiB
C
63 lines
1.7 KiB
C
/*
|
|
* Copyright (c) 2017-2023, ARM Limited and Contributors. All rights reserved.
|
|
*
|
|
* SPDX-License-Identifier: BSD-3-Clause
|
|
*/
|
|
|
|
#include <stdbool.h>
|
|
|
|
#include <arch.h>
|
|
#include <arch_helpers.h>
|
|
#include <lib/cassert.h>
|
|
#include <lib/el3_runtime/pubsub.h>
|
|
#include <lib/extensions/sve.h>
|
|
|
|
CASSERT(SVE_VECTOR_LEN <= 2048, assert_sve_vl_too_long);
|
|
CASSERT(SVE_VECTOR_LEN >= 128, assert_sve_vl_too_short);
|
|
CASSERT((SVE_VECTOR_LEN % 128) == 0, assert_sve_vl_granule);
|
|
|
|
/*
|
|
* Converts SVE vector size restriction in bytes to LEN according to ZCR_EL3 documentation.
|
|
* VECTOR_SIZE = (LEN+1) * 128
|
|
*/
|
|
#define CONVERT_SVE_LENGTH(x) (((x / 128) - 1))
|
|
|
|
void sve_enable(cpu_context_t *context)
|
|
{
|
|
u_register_t cptr_el3;
|
|
|
|
cptr_el3 = read_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3);
|
|
|
|
/* Enable access to SVE functionality for all ELs. */
|
|
cptr_el3 = (cptr_el3 | CPTR_EZ_BIT) & ~(TFP_BIT);
|
|
write_ctx_reg(get_el3state_ctx(context), CTX_CPTR_EL3, cptr_el3);
|
|
|
|
/* Restrict maximum SVE vector length (SVE_VECTOR_LEN+1) * 128. */
|
|
write_ctx_reg(get_el3state_ctx(context), CTX_ZCR_EL3,
|
|
(ZCR_EL3_LEN_MASK & CONVERT_SVE_LENGTH(SVE_VECTOR_LEN)));
|
|
}
|
|
|
|
void sve_init_el2_unused(void)
|
|
{
|
|
/*
|
|
* CPTR_EL2.TFP: Set to zero so that Non-secure accesses to Advanced
|
|
* SIMD and floating-point functionality from both Execution states do
|
|
* not trap to EL2.
|
|
*/
|
|
write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TFP_BIT);
|
|
}
|
|
|
|
void sve_disable(cpu_context_t *context)
|
|
{
|
|
u_register_t reg;
|
|
el3_state_t *state;
|
|
|
|
/* Get the context state. */
|
|
state = get_el3state_ctx(context);
|
|
|
|
/* Disable SVE and FPU since they share registers. */
|
|
reg = read_ctx_reg(state, CTX_CPTR_EL3);
|
|
reg &= ~CPTR_EZ_BIT; /* Trap SVE */
|
|
reg |= TFP_BIT; /* Trap FPU/SIMD */
|
|
write_ctx_reg(state, CTX_CPTR_EL3, reg);
|
|
}
|