Andre Przywara 603a0c6fae refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED ... At the moment we only support access to the trace unit by system registers (SYS_REG_TRACE) to be either unconditionally compiled in, or to be not supported at all. Add support for runtime detection (ENABLE_SYS_REG_TRACE_FOR_NS=2), by adding is_feat_sys_reg_trace_supported(). That function considers both build time settings and runtime information (if needed), and is used before we access SYS_REG_TRACE related registers. The FVP platform decided to compile in support unconditionally (=1), even though this is an optional feature, so it is not available with the FVP model's default command line. Change that to the now supported dynamic option (=2), so the right decision can be made by the code at runtime. Change-Id: I450a574a4f6bd9fc269887037049c94c906f54b2 Signed-off-by: Andre Przywara <andre.przywara@arm.com>		2023-03-22 13:33:22 +00:00
..
build-internals.rst	build: restrict usage of CTX_INCLUDE_EL2_REGS	2022-12-01 12:04:40 +02:00
build-options.rst	refactor(cpufeat): enable SYS_REG_TRACE for FEAT_STATE_CHECKED	2023-03-22 13:33:22 +00:00
docs-build.rst	Merge changes If90a18ee,I02e88f8c,Iea447fb5,Ie0570481,Ieeb14cfc into integration	2022-11-16 16:18:54 +01:00
image-terminology.rst	docs(build): clarify getting started section	2022-11-16 14:06:48 +00:00
index.rst	build: restrict usage of CTX_INCLUDE_EL2_REGS	2022-12-01 12:04:40 +02:00
initial-build.rst	docs(build): clarify getting started section	2022-11-16 14:06:48 +00:00
porting-guide.rst	docs: discourage usage of weak functions	2023-03-06 19:25:41 +01:00
prerequisites.rst	fix(docs): make required compiler version == rather than >=	2023-02-13 15:57:25 +00:00
psci-lib-integration-guide.rst	docs: document do_panic() and panic() helper functions	2022-11-08 14:09:33 +00:00
rt-svc-writers-guide.rst	docs(rme): add description of TF-A changes for RME	2021-11-15 22:20:07 +01:00
tools-build.rst	docs(build): clarify getting started section	2022-11-16 14:06:48 +00:00