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https://github.com/ARM-software/arm-trusted-firmware.git
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ccc61e1002
- Add MTK_SIP_SMC_FROM_S_EL1_TABLE to handle the SMC call from OP-TEE. - Register optee SMC ID for EMI MPU. Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Ming Huang <ming.huang@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Change-Id: I924ea85d29d4113e92d8f3d411c0fb77daa0c205
107 lines
3.7 KiB
C
107 lines
3.7 KiB
C
/*
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* Copyright (c) 2021-2023, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef EMI_MPU_H
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#define EMI_MPU_H
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#include <platform_def.h>
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#define ENABLE_EMI_MPU_SW_LOCK 1
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#define EMI_MPU_CTRL (EMI_MPU_BASE + 0x000)
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#define EMI_MPU_DBG (EMI_MPU_BASE + 0x004)
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#define EMI_MPU_SA0 (EMI_MPU_BASE + 0x100)
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#define EMI_MPU_EA0 (EMI_MPU_BASE + 0x200)
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#define EMI_MPU_SA(region) (EMI_MPU_SA0 + (region * 4))
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#define EMI_MPU_EA(region) (EMI_MPU_EA0 + (region * 4))
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#define EMI_MPU_APC0 (EMI_MPU_BASE + 0x300)
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#define EMI_MPU_APC(region, dgroup) (EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100))
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#define EMI_MPU_CTRL_D0 (EMI_MPU_BASE + 0x800)
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#define EMI_MPU_CTRL_D(domain) (EMI_MPU_CTRL_D0 + (domain * 4))
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#define EMI_RG_MASK_D0 (EMI_MPU_BASE + 0x900)
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#define EMI_RG_MASK_D(domain) (EMI_RG_MASK_D0 + (domain * 4))
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#define EMI_MPU_START (0x000)
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#define EMI_MPU_END (0x93C)
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#define SUB_EMI_MPU_CTRL (SUB_EMI_MPU_BASE + 0x000)
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#define SUB_EMI_MPU_DBG (SUB_EMI_MPU_BASE + 0x004)
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#define SUB_EMI_MPU_SA0 (SUB_EMI_MPU_BASE + 0x100)
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#define SUB_EMI_MPU_EA0 (SUB_EMI_MPU_BASE + 0x200)
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#define SUB_EMI_MPU_SA(region) (SUB_EMI_MPU_SA0 + (region * 4))
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#define SUB_EMI_MPU_EA(region) (SUB_EMI_MPU_EA0 + (region * 4))
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#define SUB_EMI_MPU_APC0 (SUB_EMI_MPU_BASE + 0x300)
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#define SUB_EMI_MPU_APC(region, dgroup) (SUB_EMI_MPU_APC0 + (region * 4) + (dgroup * 0x100))
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#define SUB_EMI_MPU_CTRL_D0 (SUB_EMI_MPU_BASE + 0x800)
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#define SUB_EMI_MPU_CTRL_D(domain) (SUB_EMI_MPU_CTRL_D0 + (domain * 4))
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#define SUB_EMI_RG_MASK_D0 (SUB_EMI_MPU_BASE + 0x900)
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#define SUB_EMI_RG_MASK_D(domain) (SUB_EMI_RG_MASK_D0 + (domain * 4))
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#define EMI_MPU_DOMAIN_NUM (16)
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#define EMI_MPU_REGION_NUM (32)
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#define EMI_MPU_ALIGN_BITS (16)
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#define DRAM_OFFSET (0x40000000 >> EMI_MPU_ALIGN_BITS)
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#define NO_PROTECTION 0
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#define SEC_RW 1
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#define SEC_RW_NSEC_R 2
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#define SEC_RW_NSEC_W 3
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#define SEC_R_NSEC_R 4
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#define FORBIDDEN 5
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#define SEC_R_NSEC_RW 6
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#define LOCK 1
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#define UNLOCK 0
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#define EMI_MPU_DGROUP_NUM (EMI_MPU_DOMAIN_NUM / 8)
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#if (EMI_MPU_DGROUP_NUM == 1)
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#define SET_ACCESS_PERMISSION(apc_ary, lock, d7, d6, d5, d4, d3, d2, d1, d0) \
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do { \
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apc_ary[1] = 0; \
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apc_ary[0] = \
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(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \
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(((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \
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(((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
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(((unsigned int) d1) << 3) | ((unsigned int) d0) | \
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((unsigned int) lock << 31); \
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} while (0)
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#elif (EMI_MPU_DGROUP_NUM == 2)
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#define SET_ACCESS_PERMISSION(apc_ary, lock, d15, d14, d13, d12, d11, d10, \
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d9, d8, d7, d6, d5, d4, d3, d2, d1, d0) \
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do { \
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apc_ary[1] = \
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(((unsigned int) d15) << 21) | (((unsigned int) d14) << 18) | \
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(((unsigned int) d13) << 15) | (((unsigned int) d12) << 12) | \
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(((unsigned int) d11) << 9) | (((unsigned int) d10) << 6) | \
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(((unsigned int) d9) << 3) | ((unsigned int) d8); \
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apc_ary[0] = \
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(((unsigned int) d7) << 21) | (((unsigned int) d6) << 18) | \
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(((unsigned int) d5) << 15) | (((unsigned int) d4) << 12) | \
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(((unsigned int) d3) << 9) | (((unsigned int) d2) << 6) | \
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(((unsigned int) d1) << 3) | ((unsigned int) d0) | \
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((unsigned int) lock << 31); \
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} while (0)
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#endif
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struct emi_region_info_t {
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unsigned long long start;
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unsigned long long end;
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unsigned int region;
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unsigned int apc[EMI_MPU_DGROUP_NUM];
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};
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enum MPU_REQ_ORIGIN_ZONE_ID {
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MPU_REQ_ORIGIN_TEE_ZONE_SVP = 0,
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MPU_REQ_ORIGIN_TEE_ZONE_TUI = 1,
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MPU_REQ_ORIGIN_TEE_ZONE_WFD = 2,
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MPU_REQ_ORIGIN_TEE_ZONE_MAX = 3,
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MPU_REQ_ORIGIN_ZONE_INVALID = 0x7FFFFFFF,
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};
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void emi_mpu_init(void);
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int32_t emi_mpu_sip_handler(uint64_t encoded_addr, uint64_t zone_size, uint64_t zone_info);
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#endif
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