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5fb061e761
For v8-R64, especially R82, creating code to run BL1 at EL2, using MPU. Signed-off-by: Gary Morrison <gary.morrison@arm.com> Change-Id: I439ac3915b982ad1e61d24365bdd1584b3070425
149 lines
3.4 KiB
C
149 lines
3.4 KiB
C
/*
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* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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/* Use the xlat_tables_v2 data structures: */
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#define XLAT_TABLES_LIB_V2 1
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#include <assert.h>
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#include "../../../../lib/xlat_mpu/xlat_mpu.h"
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#include <bl1/bl1.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <drivers/arm/sp805.h>
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#include "fvp_r_private.h"
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#include <plat/arm/common/arm_config.h>
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#include <plat/arm/common/arm_def.h>
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#include <plat/arm/common/plat_arm.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
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bl1_tzram_layout.total_base, \
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bl1_tzram_layout.total_size, \
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MT_MEMORY | MT_RW | MT_SECURE)
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/*
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* If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
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* otherwise one region is defined containing both
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*/
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#if SEPARATE_CODE_AND_RODATA
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#define MAP_BL1_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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BL1_CODE_END - BL_CODE_BASE, \
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MT_CODE | MT_SECURE), \
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MAP_REGION_FLAT( \
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BL1_RO_DATA_BASE, \
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BL1_RO_DATA_END \
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- BL_RO_DATA_BASE, \
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MT_RO_DATA | MT_SECURE)
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#else
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#define MAP_BL1_RO MAP_REGION_FLAT( \
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BL_CODE_BASE, \
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BL1_CODE_END - BL_CODE_BASE, \
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MT_CODE | MT_SECURE)
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#endif
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/* Data structure which holds the extents of the trusted SRAM for BL1*/
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static meminfo_t bl1_tzram_layout;
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struct meminfo *bl1_plat_sec_mem_layout(void)
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{
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return &bl1_tzram_layout;
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}
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void arm_bl1_early_platform_setup(void)
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{
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#if !ARM_DISABLE_TRUSTED_WDOG
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/* Enable watchdog */
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plat_arm_secure_wdt_start();
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#endif
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/* Initialize the console to provide early debug support */
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arm_console_boot_init();
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/* Allow BL1 to see the whole Trusted RAM */
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bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
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bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
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}
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/*******************************************************************************
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* Perform any BL1 specific platform actions.
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******************************************************************************/
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void bl1_early_platform_setup(void)
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{
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arm_bl1_early_platform_setup();
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/* Initialize the platform config for future decision making */
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fvp_config_setup();
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/*
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* Initialize Interconnect for this cluster during cold boot.
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* No need for locks as no other CPU is active.
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*/
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fvp_interconnect_init();
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/*
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* Enable coherency in Interconnect for the primary CPU's cluster.
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*/
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fvp_interconnect_enable();
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}
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void arm_bl1_plat_arch_setup(void)
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{
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const mmap_region_t bl_regions[] = {
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MAP_BL1_TOTAL,
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MAP_BL1_RO,
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#if USE_ROMLIB
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ARM_MAP_ROMLIB_CODE,
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ARM_MAP_ROMLIB_DATA,
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#endif
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#if ARM_CRYPTOCELL_INTEG
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ARM_MAP_BL_COHERENT_RAM,
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#endif
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/* DRAM1_region: */
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MAP_REGION_FLAT( \
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PLAT_ARM_DRAM1_BASE, \
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PLAT_ARM_DRAM1_SIZE, \
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MT_MEMORY | MT_SECURE | MT_EXECUTE \
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| MT_RW | MT_NON_CACHEABLE),
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/* NULL terminator: */
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{0}
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};
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setup_page_tables(bl_regions, plat_arm_get_mmap());
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enable_mpu_el2(0);
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arm_setup_romlib();
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}
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void plat_arm_secure_wdt_start(void)
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{
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sp805_start(ARM_SP805_TWDG_BASE, ARM_TWDG_LOAD_VAL);
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}
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void plat_arm_secure_wdt_stop(void)
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{
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sp805_stop(ARM_SP805_TWDG_BASE);
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}
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void bl1_platform_setup(void)
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{
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arm_bl1_platform_setup();
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/* Initialize System level generic or SP804 timer */
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fvp_timer_init();
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}
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__dead2 void bl1_plat_fwu_done(void *client_cookie, void *reserved)
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{
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/* Setup the watchdog to reset the system as soon as possible */
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sp805_refresh(ARM_SP805_TWDG_BASE, 1U);
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while (true) {
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wfi();
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}
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}
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