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5f802c8832
Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and Cortex-A78C. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I5c838f5b9d595ed3c461a7452bd465bd54acc548
108 lines
2.9 KiB
ArmAsm
108 lines
2.9 KiB
ArmAsm
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78c.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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#include "wa_cve_2022_23960_bhb_vector.S"
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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#if WORKAROUND_CVE_2022_23960
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wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
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#endif /* WORKAROUND_CVE_2022_23960 */
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A78C
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* -------------------------------------------------
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*/
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func cortex_a78c_reset_func
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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/*
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* The Cortex-A78c generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a78c
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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isb
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ret
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endfunc cortex_a78c_reset_func
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a78c_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a78c_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A78C. Must follow AAPCS.
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*/
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func cortex_a78c_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a78c_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a78c specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a78c_regs, "aS"
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cortex_a78c_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78c_cpu_reg_dump
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adr x6, cortex_a78c_regs
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mrs x8, CORTEX_A78C_CPUECTLR_EL1
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ret
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endfunc cortex_a78c_cpu_reg_dump
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declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
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cortex_a78c_reset_func, \
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cortex_a78c_core_pwr_dwn
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