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5f802c8832
Implements the loop workaround for Cortex-A76AE, Cortex-A78AE and Cortex-A78C. Signed-off-by: Bipin Ravi <bipin.ravi@arm.com> Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com> Change-Id: I5c838f5b9d595ed3c461a7452bd465bd54acc548
28 lines
836 B
C
28 lines
836 B
C
/*
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* Copyright (c) 2019-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A76AE_H
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#define CORTEX_A76AE_H
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#include <lib/utils_def.h>
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/* Cortex-A76AE MIDR for revision 0 */
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#define CORTEX_A76AE_MIDR U(0x410FD0E0)
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/* Cortex-A76 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A76AE_BHB_LOOP_COUNT U(24)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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/* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */
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#define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1)
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#define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4
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#endif /* CORTEX_A76AE_H */
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