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https://github.com/ARM-software/arm-trusted-firmware.git
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5e91007424
This patch prepares the per-cpu pointer cache for wider use by: * renaming the structure to cpu_data and placing in new header * providing accessors for this CPU, or other CPUs * splitting the initialization of the TPIDR pointer from the initialization of the cpu_data content * moving the crash stack initialization to a crash stack function * setting the TPIDR pointer very early during boot Change-Id: Icef9004ff88f8eb241d48c14be3158087d7e49a3
312 lines
9 KiB
ArmAsm
312 lines
9 KiB
ArmAsm
/*
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* Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <context.h>
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#include <cpu_data.h>
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#include <plat_macros.S>
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#include <platform_def.h>
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.globl dump_state_and_die
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.globl dump_intr_state_and_die
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.globl init_crash_reporting
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#if CRASH_REPORTING
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/* ------------------------------------------------------
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* The below section deals with dumping the system state
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* when an unhandled exception is taken in EL3.
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* The layout and the names of the registers which will
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* be dumped during a unhandled exception is given below.
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* ------------------------------------------------------
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*/
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.section .rodata.dump_reg_name, "aS"
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caller_saved_regs: .asciz "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7",\
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"x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", "x16",\
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"x17", "x18", ""
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callee_saved_regs: .asciz "x19", "x20", "x21", "x22", "x23", "x24",\
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"x25", "x26", "x27", "x28", "x29", "x30", ""
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el3_sys_regs: .asciz "scr_el3", "sctlr_el3", "cptr_el3", "tcr_el3",\
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"daif", "mair_el3", "spsr_el3", "elr_el3", "ttbr0_el3", "esr_el3",\
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"sp_el3", "far_el3", ""
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non_el3_sys_0_regs: .asciz "spsr_el1", "elr_el1", "spsr_abt", "spsr_und",\
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"spsr_irq", "spsr_fiq", "sctlr_el1", "actlr_el1", "cpacr_el1",\
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"csselr_el1", "sp_el1", "esr_el1", "ttbr0_el1", "ttbr1_el1",\
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"mair_el1", "amair_el1", "tcr_el1", "tpidr_el1", ""
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non_el3_sys_1_regs: .asciz "tpidr_el0", "tpidrro_el0", "dacr32_el2",\
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"ifsr32_el2", "par_el1", "far_el1", "afsr0_el1", "afsr1_el1",\
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"contextidr_el1", "vbar_el1", "cntp_ctl_el0", "cntp_cval_el0",\
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"cntv_ctl_el0", "cntv_cval_el0", "cntkctl_el1", "fpexc32_el2",\
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"sp_el0", ""
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/* -----------------------------------------------------
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* Currently we are stack limited. Hence make sure that
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* we dont try to dump more than 20 registers using the
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* stack.
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* -----------------------------------------------------
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*/
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#define REG_SIZE 0x8
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/* The caller saved registers are X0 to X18 */
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#define CALLER_SAVED_REG_SIZE (20 * REG_SIZE)
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/* The caller saved registers are X19 to X30 */
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#define CALLEE_SAVED_REG_SIZE (12 * REG_SIZE)
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/* The EL3 sys regs*/
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#define EL3_SYS_REG_SIZE (12 * REG_SIZE)
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/* The non EL3 sys regs set-0 */
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#define NON_EL3_SYS_0_REG_SIZE (18 * REG_SIZE)
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/* The non EL3 sys regs set-1 */
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#define NON_EL3_SYS_1_REG_SIZE (18 * REG_SIZE)
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.macro print_caller_saved_regs
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sub sp, sp, #CALLER_SAVED_REG_SIZE
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stp x0, x1, [sp]
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stp x2, x3, [sp, #(REG_SIZE * 2)]
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stp x4, x5, [sp, #(REG_SIZE * 4)]
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stp x6, x7, [sp, #(REG_SIZE * 6)]
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stp x8, x9, [sp, #(REG_SIZE * 8)]
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stp x10, x11, [sp, #(REG_SIZE * 10)]
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stp x12, x13, [sp, #(REG_SIZE * 12)]
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stp x14, x15, [sp, #(REG_SIZE * 14)]
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stp x16, x17, [sp, #(REG_SIZE * 16)]
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stp x18, xzr, [sp, #(REG_SIZE * 18)]
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adr x0, caller_saved_regs
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mov x1, sp
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bl print_string_value
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add sp, sp, #CALLER_SAVED_REG_SIZE
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.endm
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.macro print_callee_saved_regs
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sub sp, sp, CALLEE_SAVED_REG_SIZE
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stp x19, x20, [sp]
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stp x21, x22, [sp, #(REG_SIZE * 2)]
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stp x23, x24, [sp, #(REG_SIZE * 4)]
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stp x25, x26, [sp, #(REG_SIZE * 6)]
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stp x27, x28, [sp, #(REG_SIZE * 8)]
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stp x29, x30, [sp, #(REG_SIZE * 10)]
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adr x0, callee_saved_regs
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mov x1, sp
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bl print_string_value
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add sp, sp, #CALLEE_SAVED_REG_SIZE
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.endm
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.macro print_el3_sys_regs
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sub sp, sp, #EL3_SYS_REG_SIZE
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mrs x9, scr_el3
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mrs x10, sctlr_el3
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mrs x11, cptr_el3
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mrs x12, tcr_el3
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mrs x13, daif
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mrs x14, mair_el3
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mrs x15, spsr_el3 /*save the elr and spsr regs seperately*/
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mrs x16, elr_el3
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mrs x17, ttbr0_el3
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mrs x8, esr_el3
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mrs x7, far_el3
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stp x9, x10, [sp]
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stp x11, x12, [sp, #(REG_SIZE * 2)]
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stp x13, x14, [sp, #(REG_SIZE * 4)]
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stp x15, x16, [sp, #(REG_SIZE * 6)]
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stp x17, x8, [sp, #(REG_SIZE * 8)]
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stp x0, x7, [sp, #(REG_SIZE * 10)] /* sp_el3 is in x0 */
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adr x0, el3_sys_regs
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mov x1, sp
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bl print_string_value
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add sp, sp, #EL3_SYS_REG_SIZE
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.endm
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.macro print_non_el3_sys_0_regs
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sub sp, sp, #NON_EL3_SYS_0_REG_SIZE
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mrs x9, spsr_el1
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mrs x10, elr_el1
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mrs x11, spsr_abt
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mrs x12, spsr_und
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mrs x13, spsr_irq
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mrs x14, spsr_fiq
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mrs x15, sctlr_el1
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mrs x16, actlr_el1
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mrs x17, cpacr_el1
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mrs x8, csselr_el1
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stp x9, x10, [sp]
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stp x11, x12, [sp, #(REG_SIZE * 2)]
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stp x13, x14, [sp, #(REG_SIZE * 4)]
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stp x15, x16, [sp, #(REG_SIZE * 6)]
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stp x17, x8, [sp, #(REG_SIZE * 8)]
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mrs x10, sp_el1
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mrs x11, esr_el1
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mrs x12, ttbr0_el1
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mrs x13, ttbr1_el1
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mrs x14, mair_el1
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mrs x15, amair_el1
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mrs x16, tcr_el1
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mrs x17, tpidr_el1
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stp x10, x11, [sp, #(REG_SIZE * 10)]
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stp x12, x13, [sp, #(REG_SIZE * 12)]
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stp x14, x15, [sp, #(REG_SIZE * 14)]
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stp x16, x17, [sp, #(REG_SIZE * 16)]
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adr x0, non_el3_sys_0_regs
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mov x1, sp
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bl print_string_value
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add sp, sp, #NON_EL3_SYS_0_REG_SIZE
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.endm
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.macro print_non_el3_sys_1_regs
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sub sp, sp, #NON_EL3_SYS_1_REG_SIZE
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mrs x9, tpidr_el0
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mrs x10, tpidrro_el0
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mrs x11, dacr32_el2
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mrs x12, ifsr32_el2
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mrs x13, par_el1
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mrs x14, far_el1
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mrs x15, afsr0_el1
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mrs x16, afsr1_el1
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mrs x17, contextidr_el1
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mrs x8, vbar_el1
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stp x9, x10, [sp]
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stp x11, x12, [sp, #(REG_SIZE * 2)]
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stp x13, x14, [sp, #(REG_SIZE * 4)]
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stp x15, x16, [sp, #(REG_SIZE * 6)]
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stp x17, x8, [sp, #(REG_SIZE * 8)]
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mrs x10, cntp_ctl_el0
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mrs x11, cntp_cval_el0
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mrs x12, cntv_ctl_el0
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mrs x13, cntv_cval_el0
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mrs x14, cntkctl_el1
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mrs x15, fpexc32_el2
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mrs x8, sp_el0
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stp x10, x11, [sp, #(REG_SIZE *10)]
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stp x12, x13, [sp, #(REG_SIZE * 12)]
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stp x14, x15, [sp, #(REG_SIZE * 14)]
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stp x8, xzr, [sp, #(REG_SIZE * 16)]
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adr x0, non_el3_sys_1_regs
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mov x1, sp
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bl print_string_value
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add sp, sp, #NON_EL3_SYS_1_REG_SIZE
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.endm
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.macro init_crash_stack
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msr cntfrq_el0, x0 /* we can corrupt this reg to free up x0 */
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mrs x0, tpidr_el3
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/* Check if tpidr is initialized */
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cbz x0, infinite_loop
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ldr x0, [x0, #CPU_DATA_CRASH_STACK_OFFSET]
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/* store the x30 and sp to stack */
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str x30, [x0, #-(REG_SIZE)]!
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mov x30, sp
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str x30, [x0, #-(REG_SIZE)]!
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mov sp, x0
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mrs x0, cntfrq_el0
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.endm
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/* ---------------------------------------------------
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* The below function initializes the crash dump stack ,
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* and prints the system state. This function
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* will not return.
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* ---------------------------------------------------
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*/
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func dump_state_and_die
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init_crash_stack
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print_caller_saved_regs
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b print_state
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func dump_intr_state_and_die
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init_crash_stack
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print_caller_saved_regs
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plat_print_gic_regs /* fall through to print_state */
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print_state:
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/* copy the original x30 from stack */
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ldr x30, [sp, #REG_SIZE]
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print_callee_saved_regs
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/* copy the original SP_EL3 from stack to x0 and rewind stack */
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ldr x0, [sp], #(REG_SIZE * 2)
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print_el3_sys_regs
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print_non_el3_sys_0_regs
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print_non_el3_sys_1_regs
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#else /* CRASH_REPORING */
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func dump_state_and_die
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dump_intr_state_and_die:
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#endif /* CRASH_REPORING */
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infinite_loop:
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b infinite_loop
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#define PCPU_CRASH_STACK_SIZE 0x140
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/* -----------------------------------------------------
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* Per-cpu crash stacks in normal memory.
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* -----------------------------------------------------
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*/
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declare_stack pcpu_crash_stack, tzfw_normal_stacks, \
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PCPU_CRASH_STACK_SIZE, PLATFORM_CORE_COUNT
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/* -----------------------------------------------------
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* Provides each CPU with a small stacks for reporting
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* unhandled exceptions, and stores the stack address
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* in cpu_data
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*
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* This can be called without a runtime stack
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* clobbers: x0 - x4
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* -----------------------------------------------------
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*/
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func init_crash_reporting
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mov x4, x30
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mov x2, #0
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adr x3, pcpu_crash_stack
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init_crash_loop:
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mov x0, x2
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bl _cpu_data_by_index
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add x3, x3, #PCPU_CRASH_STACK_SIZE
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str x3, [x0, #CPU_DATA_CRASH_STACK_OFFSET]
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add x2, x2, #1
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cmp x2, #PLATFORM_CORE_COUNT
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b.lo init_crash_loop
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ret x4
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