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Various CPU drivers in ARM Trusted Firmware register functions to handle power-down operations. At present, separate functions are registered to power down individual cores and clusters. This scheme operates on the basis of core and cluster, and doesn't cater for extending the hierarchy for power-down operations. For example, future CPUs might support multiple threads which might need powering down individually. This patch therefore reworks the CPU operations framework to allow for registering power down handlers on specific level basis. Henceforth: - Generic code invokes CPU power down operations by the level required. - CPU drivers explicitly mention CPU_NO_RESET_FUNC when the CPU has no reset function. - CPU drivers register power down handlers as a list: a mandatory handler for level 0, and optional handlers for higher levels. All existing CPU drivers are adapted to the new CPU operations framework without needing any functional changes within. Also update firmware design guide. Change-Id: I1826842d37a9e60a9e85fdcee7b4b8f6bc1ad043 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
228 lines
6.2 KiB
ArmAsm
228 lines
6.2 KiB
ArmAsm
/*
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* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cpu_macros.S>
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#if IMAGE_BL31
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#include <cpu_data.h>
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#endif
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#include <debug.h>
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/* Reset fn is needed in BL at reset vector */
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#if IMAGE_BL1 || IMAGE_BL31
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/*
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* The reset handler common to all platforms. After a matching
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* cpu_ops structure entry is found, the correponding reset_handler
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* in the cpu_ops is invoked.
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* Clobbers: x0 - x19, x30
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*/
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.globl reset_handler
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func reset_handler
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mov x19, x30
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/* The plat_reset_handler can clobber x0 - x18, x30 */
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bl plat_reset_handler
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/* Get the matching cpu_ops pointer */
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bl get_cpu_ops_ptr
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#if ASM_ASSERTION
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the cpu_ops reset handler */
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ldr x2, [x0, #CPU_RESET_FUNC]
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mov x30, x19
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cbz x2, 1f
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/* The cpu_ops reset handler can clobber x0 - x19, x30 */
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br x2
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1:
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ret
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endfunc reset_handler
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#endif /* IMAGE_BL1 || IMAGE_BL31 */
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#if IMAGE_BL31 /* The power down core and cluster is needed only in BL31 */
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/*
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* void prepare_cpu_pwr_dwn(unsigned int power_level)
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*
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* Prepare CPU power down function for all platforms. The function takes
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* a domain level to be powered down as its parameter. After the cpu_ops
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* pointer is retrieved from cpu_data, the handler for requested power
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* level is called.
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*/
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.globl prepare_cpu_pwr_dwn
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func prepare_cpu_pwr_dwn
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/*
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* If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
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* power down handler for the last power level
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*/
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mov_imm x2, (CPU_MAX_PWR_DWN_OPS - 1)
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cmp x0, x2
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csel x2, x2, x0, hi
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mrs x1, tpidr_el3
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ldr x0, [x1, #CPU_DATA_CPU_OPS_PTR]
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#if ASM_ASSERTION
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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/* Get the appropriate power down handler */
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mov x1, #CPU_PWR_DWN_OPS
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add x1, x1, x2, lsl #3
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ldr x1, [x0, x1]
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br x1
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endfunc prepare_cpu_pwr_dwn
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/*
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* Initializes the cpu_ops_ptr if not already initialized
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* in cpu_data. This can be called without a runtime stack, but may
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* only be called after the MMU is enabled.
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* clobbers: x0 - x6, x10
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*/
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.globl init_cpu_ops
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func init_cpu_ops
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mrs x6, tpidr_el3
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ldr x0, [x6, #CPU_DATA_CPU_OPS_PTR]
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cbnz x0, 1f
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mov x10, x30
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bl get_cpu_ops_ptr
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#if ASM_ASSERTION
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cmp x0, #0
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ASM_ASSERT(ne)
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#endif
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str x0, [x6, #CPU_DATA_CPU_OPS_PTR]!
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mov x30, x10
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1:
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ret
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endfunc init_cpu_ops
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#endif /* IMAGE_BL31 */
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#if IMAGE_BL31 && CRASH_REPORTING
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/*
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* The cpu specific registers which need to be reported in a crash
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* are reported via cpu_ops cpu_reg_dump function. After a matching
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* cpu_ops structure entry is found, the correponding cpu_reg_dump
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* in the cpu_ops is invoked.
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*/
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.globl do_cpu_reg_dump
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func do_cpu_reg_dump
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mov x16, x30
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/* Get the matching cpu_ops pointer */
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bl get_cpu_ops_ptr
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cbz x0, 1f
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/* Get the cpu_ops cpu_reg_dump */
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ldr x2, [x0, #CPU_REG_DUMP]
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cbz x2, 1f
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blr x2
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1:
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mov x30, x16
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ret
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endfunc do_cpu_reg_dump
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#endif
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/*
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* The below function returns the cpu_ops structure matching the
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* midr of the core. It reads the MIDR_EL1 and finds the matching
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* entry in cpu_ops entries. Only the implementation and part number
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* are used to match the entries.
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* Return :
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* x0 - The matching cpu_ops pointer on Success
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* x0 - 0 on failure.
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* Clobbers : x0 - x5
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*/
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.globl get_cpu_ops_ptr
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func get_cpu_ops_ptr
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/* Get the cpu_ops start and end locations */
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adr x4, (__CPU_OPS_START__ + CPU_MIDR)
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adr x5, (__CPU_OPS_END__ + CPU_MIDR)
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/* Initialize the return parameter */
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mov x0, #0
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/* Read the MIDR_EL1 */
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mrs x2, midr_el1
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mov_imm x3, CPU_IMPL_PN_MASK
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/* Retain only the implementation and part number using mask */
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and w2, w2, w3
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1:
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/* Check if we have reached end of list */
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cmp x4, x5
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b.eq error_exit
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/* load the midr from the cpu_ops */
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ldr x1, [x4], #CPU_OPS_SIZE
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and w1, w1, w3
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/* Check if midr matches to midr of this core */
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cmp w1, w2
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b.ne 1b
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/* Subtract the increment and offset to get the cpu-ops pointer */
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sub x0, x4, #(CPU_OPS_SIZE + CPU_MIDR)
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error_exit:
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ret
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endfunc get_cpu_ops_ptr
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#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
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.section .rodata.rev_verbose_str, "aS"
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rev_verbose_str:
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.asciz "VERBOSE: Skipping CPU specific reset operation for non-matching CPU revision number.\n"
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/*
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* This function prints the above warning message to the crash console.
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* It should be called when a CPU specific operation is enabled in the
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* build but doesn't apply to this CPU revision/part number.
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*
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* Clobber: x30, x0 - x5
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*/
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.globl print_revision_warning
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func print_revision_warning
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mov x5, x30
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/* Ensure the console is initialized */
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bl plat_crash_console_init
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/* Check if the console is initialized */
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cbz x0, 1f
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/* The console is initialized */
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adr x4, rev_verbose_str
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bl asm_print_str
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1:
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ret x5
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endfunc print_revision_warning
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#endif
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