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https://github.com/ARM-software/arm-trusted-firmware.git
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646a9a1615
Agilex5 platform: Boot scratch COLD6 register is meant for Customer use only. So, use Intel specific COLD3 register with [5:2]bits to determine the warm reset and SMP boot requests. Also handle the unaligned DEVICE/IO memory store and load in the assembly entrypoint startup code. Agilex, Stratix10, N5X platforms: Use only the LSB 4bits [3:0] of the boot scratch COLD6 register to detect the warm reset request. Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
221 lines
7.9 KiB
C
221 lines
7.9 KiB
C
/*
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* Copyright (c) 2019-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <common/interrupt_props.h>
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#include <common/tbbr/tbbr_img_def.h>
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#include <plat/common/common_def.h>
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#include "socfpga_plat_def.h"
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/* Platform Type */
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#define PLAT_SOCFPGA_STRATIX10 1
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#define PLAT_SOCFPGA_AGILEX 2
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#define PLAT_SOCFPGA_N5X 3
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#define PLAT_SOCFPGA_AGILEX5 4
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#define SIMICS_RUN 1
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#define MAX_IO_MTD_DEVICES U(1)
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/* Boot Source configuration
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* TODO: Shall consider "assert_numeric" in the future
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*/
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#if SOCFPGA_BOOT_SOURCE_NAND
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#define BOOT_SOURCE BOOT_SOURCE_NAND
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#elif SOCFPGA_BOOT_SOURCE_SDMMC
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#elif SOCFPGA_BOOT_SOURCE_QSPI
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#define BOOT_SOURCE BOOT_SOURCE_QSPI
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#else
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#define BOOT_SOURCE BOOT_SOURCE_SDMMC
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#endif
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/* sysmgr.boot_scratch_cold4 & 5 used for CPU release address for SPL */
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#define PLAT_CPU_RELEASE_ADDR 0xffd12210
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/* Define next boot image name and offset */
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/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
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#ifdef PRELOADED_BL33_BASE
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#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
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#else
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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#define PLAT_NS_IMAGE_OFFSET 0x80200000
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#else
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#define PLAT_NS_IMAGE_OFFSET 0x10000000
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#endif
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#endif /* #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 */
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#define PLAT_QSPI_DATA_BASE (0x3C00000)
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#define PLAT_NAND_DATA_BASE (0x0200000)
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#define PLAT_SDMMC_DATA_BASE (0x0)
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/*******************************************************************************
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* Platform binary types for linking
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******************************************************************************/
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#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
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#define PLATFORM_LINKER_ARCH aarch64
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/* SoCFPGA supports up to 124GB RAM */
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x2000
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/* PSCI related constant */
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#define PLAT_NUM_POWER_DOMAINS 5
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#define PLAT_MAX_PWR_LVL 1
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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#define PLATFORM_SYSTEM_COUNT U(1)
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#define PLATFORM_CLUSTER_COUNT U(1)
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#define PLATFORM_CLUSTER0_CORE_COUNT U(4)
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#define PLATFORM_CLUSTER1_CORE_COUNT U(0)
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
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PLATFORM_CLUSTER0_CORE_COUNT)
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#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
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/* Interrupt related constant */
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#define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14
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#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15
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#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER
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#define TSP_SEC_MEM_BASE BL32_BASE
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#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
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* little space for growth.
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*/
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define BL1_RO_BASE (0xffe00000)
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#define BL1_RO_LIMIT (0xffe0f000)
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#define BL1_RW_BASE (0xffe10000)
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#define BL1_RW_LIMIT (0xffe1ffff)
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#define BL1_RW_SIZE (0x14000)
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#define BL_DATA_LIMIT PLAT_HANDOFF_OFFSET
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#define PLAT_CPUID_RELEASE (BL_DATA_LIMIT - 16)
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#define PLAT_SEC_ENTRY (BL_DATA_LIMIT - 8)
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#define CMP_ENTRY 0xFFE3EFF8
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#define PLAT_SEC_WARM_ENTRY 0
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define MAX_XLAT_TABLES 8
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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******************************************************************************/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
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#define PLAT_INTEL_UART_BASE PLAT_UART0_BASE
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#define PLAT_BAUDRATE (115200)
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#define PLAT_UART_CLOCK (100000000)
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/*******************************************************************************
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* PHY related constants
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******************************************************************************/
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#define EMAC0_PHY_MODE PHY_INTERFACE_MODE_RGMII
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#define EMAC1_PHY_MODE PHY_INTERFACE_MODE_RGMII
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#define EMAC2_PHY_MODE PHY_INTERFACE_MODE_RGMII
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/*******************************************************************************
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* GIC related constants
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******************************************************************************/
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#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE
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#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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/*
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* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
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* terminology. On a GICv2 system or mode, the lists will be merged and treated
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* as Group 0 interrupts.
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*/
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#define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
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INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \
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GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE)
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#define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp)
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#define MAX_IO_HANDLES 4
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#define MAX_IO_DEVICES 4
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#define MAX_IO_BLOCK_DEVICES 2
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#ifndef __ASSEMBLER__
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struct socfpga_bl31_params {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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};
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#endif
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#endif /* PLATFORM_DEF_H */
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