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646a9a1615
Agilex5 platform: Boot scratch COLD6 register is meant for Customer use only. So, use Intel specific COLD3 register with [5:2]bits to determine the warm reset and SMP boot requests. Also handle the unaligned DEVICE/IO memory store and load in the assembly entrypoint startup code. Agilex, Stratix10, N5X platforms: Use only the LSB 4bits [3:0] of the boot scratch COLD6 register to detect the warm reset request. Change-Id: I4fd6e63fe0bd42ddcb4a3f81c7a7295bdc8ca65f Signed-off-by: Girisha Dengi <girisha.dengi@intel.com> Signed-off-by: Jit Loon Lim <jit.loon.lim@altera.com>
282 lines
7 KiB
ArmAsm
282 lines
7 KiB
ArmAsm
/*
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* Copyright (c) 2019-2023, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <cpu_macros.S>
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#include <platform_def.h>
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#include <el3_common_macros.S>
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.globl plat_secondary_cold_boot_setup
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.globl platform_is_primary_cpu
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl plat_crash_console_flush
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.globl platform_mem_init
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.globl plat_secondary_cpus_bl31_entry
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.globl plat_get_my_entrypoint
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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/* Wait until the it gets reset signal from rstmgr gets populated */
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poll_mailbox:
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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mov_imm x0, PLAT_SEC_ENTRY
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cbz x0, poll_mailbox
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br x0
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#else
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wfi
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mov_imm x0, PLAT_SEC_ENTRY
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ldr x1, [x0]
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mov_imm x2, PLAT_CPUID_RELEASE
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ldr x3, [x2]
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mrs x4, mpidr_el1
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and x4, x4, #0xff
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cmp x3, x4
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b.ne poll_mailbox
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br x1
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#endif
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endfunc plat_secondary_cold_boot_setup
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#if ((PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10) || \
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(PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX) || \
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(PLATFORM_MODEL == PLAT_SOCFPGA_N5X))
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func platform_is_primary_cpu
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #PLAT_PRIMARY_CPU
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cset x0, eq
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ret
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endfunc platform_is_primary_cpu
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#else
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func platform_is_primary_cpu
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #(PLAT_PRIMARY_CPU_A76)
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b.eq primary_cpu
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cmp x0, #(PLAT_PRIMARY_CPU_A55)
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b.eq primary_cpu
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primary_cpu:
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cset x0, eq
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ret
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endfunc platform_is_primary_cpu
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#endif
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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b platform_is_primary_cpu
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endfunc plat_is_my_cpu_primary
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func plat_my_core_pos
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mrs x0, mpidr_el1
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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add x0, x1, x0, LSR #8
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#else
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add x0, x1, x0, LSR #6
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#endif
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ret
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endfunc plat_my_core_pos
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func warm_reset_req
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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/* Clear the markup before going for warm reset */
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bic x2, x2, #BS_REG_MAGIC_KEYS_MASK
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/* Check if the address is 64 bit aligned or not */
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ldr x4, =L2_RESET_DONE_REG
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tst x4, #ALIGN_CHECK_64BIT_MASK
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b.ne unaligned_store
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/* Device memory address is aligned, store the value directly */
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str x2, [x4]
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b continue_warm_reset
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/* Unaligned store, use byte by byte method to store */
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unaligned_store:
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strb w2, [x4]
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lsr x2, x2, #8
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add x4, x4, #1
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strb w2, [x4]
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lsr x2, x2, #8
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add x4, x4, #1
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strb w2, [x4]
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lsr x2, x2, #8
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add x4, x4, #1
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strb w2, [x4]
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#else
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/* Clear the markup before going for warm reset */
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bic x2, x2, #BS_REG_MAGIC_KEYS_MASK
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str x2, [x4]
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#endif
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continue_warm_reset:
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bl plat_is_my_cpu_primary
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cbz x0, cpu_in_wfi
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mov_imm x1, PLAT_SEC_ENTRY
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str xzr, [x1]
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mrs x1, rmr_el3
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orr x1, x1, #0x02
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msr rmr_el3, x1
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isb
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dsb sy
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cpu_in_wfi:
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wfi
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b cpu_in_wfi
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endfunc warm_reset_req
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#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
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func plat_get_my_entrypoint
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ldr x4, =L2_RESET_DONE_REG
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/* Check if the address is 64 bit aligned or not */
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tst x4, #ALIGN_CHECK_64BIT_MASK
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b.ne unaligned_load
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/* Device memory address is aligned, load the value directly */
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ldr x1, [x4]
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b events_check
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/*
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* It is unaligned device memory access. Read only LSB 32 bits
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* byte by byte and combine them to get the 32 bit value.
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*/
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unaligned_load:
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ldrb w1, [x4]
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ldrb w2, [x4, #1]
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ldrb w3, [x4, #2]
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ldrb w4, [x4, #3]
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orr x1, x1, x2, lsl #8
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orr x1, x1, x3, lsl #16
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orr x1, x1, x4, lsl #24
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events_check:
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/* Keep a backup of the boot scratch register contents */
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mov x2, x1
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/* Mask and get the required bits */
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and x1, x1, #BS_REG_MAGIC_KEYS_MASK
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/* Check for warm reset request */
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ldr x5, =L2_RESET_DONE_STATUS
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cmp x1, x5
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b.eq warm_reset_req
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/* Check for SMP secondary cores boot request */
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ldr x5, =SMP_SEC_CORE_BOOT_REQ
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cmp x1, x5
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b.eq smp_request
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/* Otherwise it is a cold reset request */
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mov x0, #0
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ret
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smp_request:
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/*
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* On the SMP boot request, return the address 'bl31_warm_entrypoint',
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* which is passed to 'psci_setup' routine as part of BL31
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* initialization.
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*/
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ldr x1, =PLAT_SEC_ENTRY
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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#else
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func plat_get_my_entrypoint
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ldr x4, =L2_RESET_DONE_REG
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ldr x5, [x4]
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/* Keep a backup of the boot scratch register contents */
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mov x2, x5
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/* Mask and get only the required bits */
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and x5, x5, #BS_REG_MAGIC_KEYS_MASK
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/* Check for warm reset request */
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ldr x1, =L2_RESET_DONE_STATUS
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cmp x1, x5
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b.eq warm_reset_req
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mov_imm x1, PLAT_SEC_ENTRY
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ldr x0, [x1]
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ret
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endfunc plat_get_my_entrypoint
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#endif
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0, x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, CRASH_CONSOLE_BASE
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mov_imm x1, PLAT_UART_CLOCK
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mov_imm x2, PLAT_BAUDRATE
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b console_16550_core_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(void)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, CRASH_CONSOLE_BASE
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b console_16550_core_putc
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endfunc plat_crash_console_putc
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func plat_crash_console_flush
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mov_imm x0, CRASH_CONSOLE_BASE
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b console_16550_core_flush
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endfunc plat_crash_console_flush
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/* --------------------------------------------------------
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* void platform_mem_init (void);
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*
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* Any memory init, relocation to be done before the
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* platform boots. Called very early in the boot process.
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* --------------------------------------------------------
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*/
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func platform_mem_init
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mov x0, #0
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ret
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endfunc platform_mem_init
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/* --------------------------------------------------------
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* macro plat_secondary_cpus_bl31_entry;
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*
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* el3_entrypoint_common init param configuration.
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* Called very early in the secondary cores boot process.
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* --------------------------------------------------------
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*/
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func plat_secondary_cpus_bl31_entry
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el3_entrypoint_common \
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_init_sctlr=0 \
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_warm_boot_mailbox=!PROGRAMMABLE_RESET_ADDRESS \
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_secondary_cold_boot=!COLD_BOOT_SINGLE_CPU \
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_init_memory=1 \
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_init_c_runtime=1 \
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_exception_vectors=runtime_exceptions \
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_pie_fixup_size=BL31_LIMIT - BL31_BASE
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endfunc plat_secondary_cpus_bl31_entry
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