mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
288 lines
8.6 KiB
C
288 lines
8.6 KiB
C
/*
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* Copyright (c) 2019-2024, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
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* Copyright (c) 2024, Altera Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <arch.h>
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#include <arch_helpers.h>
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#include <common/bl_common.h>
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#include <drivers/arm/gic_common.h>
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#include <drivers/arm/gicv3.h>
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#include <drivers/ti/uart/uart_16550.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include "agilex5_cache.h"
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#include "agilex5_power_manager.h"
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#include "ccu/ncore_ccu.h"
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#include "socfpga_mailbox.h"
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#include "socfpga_private.h"
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#include "socfpga_reset_manager.h"
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/* Get non-secure SPSR for BL33. Zephyr and Linux */
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uint32_t arm_get_spsr_for_bl33_entry(void);
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static entry_point_info_t bl32_image_ep_info;
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static entry_point_info_t bl33_image_ep_info;
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/* The GICv3 driver only needs to be initialized in EL3 */
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static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
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#define SMMU_SDMMC
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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next_image_info = (type == NON_SECURE) ?
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&bl33_image_ep_info : &bl32_image_ep_info;
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/* None of the images on this platform can have 0x0 as the entrypoint */
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if (next_image_info->pc)
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return next_image_info;
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else
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return NULL;
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}
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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static console_t console;
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mmio_write_64(PLAT_SEC_ENTRY, PLAT_SEC_WARM_ENTRY);
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console_16550_register(PLAT_INTEL_UART_BASE, PLAT_UART_CLOCK,
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PLAT_BAUDRATE, &console);
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setup_smmu_stream_id();
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/*
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* Check params passed from BL31 should not be NULL,
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*/
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void *from_bl2 = (void *) arg0;
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#if RESET_TO_BL31
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/* There are no parameters from BL2 if BL31 is a reset vector */
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assert(from_bl2 == NULL);
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void *plat_params_from_bl2 = (void *) arg3;
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assert(plat_params_from_bl2 == NULL);
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/* Populate entry point information for BL33 */
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SET_PARAM_HEAD(&bl33_image_ep_info,
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PARAM_EP,
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VERSION_1,
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0);
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# if ARM_LINUX_KERNEL_AS_BL33
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/*
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* According to the file ``Documentation/arm64/booting.txt`` of the
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* Linux kernel tree, Linux expects the physical address of the device
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* tree blob (DTB) in x0, while x1-x3 are reserved for future use and
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* must be 0.
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*/
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bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
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bl33_image_ep_info.args.arg1 = 0U;
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bl33_image_ep_info.args.arg2 = 0U;
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bl33_image_ep_info.args.arg3 = 0U;
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# endif
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#else /* RESET_TO_BL31 */
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bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
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assert(params_from_bl2 != NULL);
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/*
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* Copy BL32 (if populated by BL31) and BL33 entry point information.
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* They are stored in Secure RAM, in BL31's address space.
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*/
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if (params_from_bl2->h.type == PARAM_BL_PARAMS &&
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params_from_bl2->h.version >= VERSION_2) {
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bl_params_node_t *bl_params = params_from_bl2->head;
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while (bl_params) {
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if (bl_params->image_id == BL33_IMAGE_ID) {
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bl33_image_ep_info = *bl_params->ep_info;
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}
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bl_params = bl_params->next_params_info;
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}
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} else {
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struct socfpga_bl31_params *arg_from_bl2 =
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(struct socfpga_bl31_params *) from_bl2;
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assert(arg_from_bl2->h.type == PARAM_BL31);
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assert(arg_from_bl2->h.version >= VERSION_1);
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bl32_image_ep_info = *arg_from_bl2->bl32_ep_info;
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bl33_image_ep_info = *arg_from_bl2->bl33_ep_info;
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}
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bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
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bl33_image_ep_info.args.arg1 = 0U;
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bl33_image_ep_info.args.arg2 = 0U;
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bl33_image_ep_info.args.arg3 = 0U;
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#endif
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/*
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* Tell BL31 where the non-trusted software image
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* is located and the entry state information
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*/
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bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
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bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
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SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
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}
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static const interrupt_prop_t agx5_interrupt_props[] = {
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PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(INTR_GROUP1S),
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PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(INTR_GROUP0)
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};
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static const gicv3_driver_data_t plat_gicv3_gic_data = {
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.gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
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.gicr_base = PLAT_INTEL_SOCFPGA_GICR_BASE,
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.interrupt_props = agx5_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(agx5_interrupt_props),
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.rdistif_num = PLATFORM_CORE_COUNT,
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.rdistif_base_addrs = rdistif_base_addrs,
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};
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/*******************************************************************************
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* Perform any BL3-1 platform setup code
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******************************************************************************/
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void bl31_platform_setup(void)
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{
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socfpga_delay_timer_init();
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/* Initialize the gic cpu and distributor interfaces */
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gicv3_driver_init(&plat_gicv3_gic_data);
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gicv3_distif_init();
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gicv3_rdistif_init(plat_my_core_pos());
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gicv3_cpuif_enable(plat_my_core_pos());
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mailbox_hps_stage_notify(HPS_EXECUTION_STATE_SSBL);
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}
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const mmap_region_t plat_agilex_mmap[] = {
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MAP_REGION_FLAT(DRAM_BASE, DRAM_SIZE, MT_MEMORY | MT_RW | MT_NS),
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MAP_REGION_FLAT(PSS_BASE, PSS_SIZE, MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(MPFE_BASE, MPFE_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(OCRAM_BASE, OCRAM_SIZE, MT_NON_CACHEABLE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(CCU_BASE, CCU_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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MAP_REGION_FLAT(MEM64_BASE, MEM64_SIZE, MT_DEVICE | MT_RW | MT_NS),
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MAP_REGION_FLAT(GIC_BASE, GIC_SIZE, MT_DEVICE | MT_RW | MT_SECURE),
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{0}
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};
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/*******************************************************************************
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* Perform the very early platform specific architectural setup here. At the
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* moment this is only initializes the mmu in a quick and dirty way.
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******************************************************************************/
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void bl31_plat_arch_setup(void)
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{
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uint32_t boot_core = 0x00;
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uint32_t cpuid = 0x00;
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cpuid = MPIDR_AFFLVL1_VAL(read_mpidr());
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boot_core = ((mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00) >> 10);
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NOTICE("BL31: Boot Core = %x\n", boot_core);
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NOTICE("BL31: CPU ID = %x\n", cpuid);
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INFO("BL31: Invalidate Data cache\n");
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invalidate_dcache_all();
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/* Invalidate for NS EL2 and EL1 */
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invalidate_cache_low_el();
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}
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/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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#ifdef PRELOADED_BL33_BASE
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return PRELOADED_BL33_BASE;
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#else
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return PLAT_NS_IMAGE_OFFSET;
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#endif
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}
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/* Get non-secure SPSR for BL33. Zephyr and Linux */
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uint32_t arm_get_spsr_for_bl33_entry(void)
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{
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unsigned int mode;
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uint32_t spsr;
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/* Figure out what mode we enter the non-secure world in */
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mode = (el_implemented(2) != EL_IMPL_NONE) ? MODE_EL2 : MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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spsr = SPSR_64((uint64_t)mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
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return spsr;
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}
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/* SMP: Secondary cores BL31 setup reset vector */
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void bl31_plat_set_secondary_cpu_entrypoint(unsigned int cpu_id)
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{
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unsigned int pch_cpu = 0x00;
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unsigned int pchctlr_old = 0x00;
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unsigned int pchctlr_new = 0x00;
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uint32_t boot_core = 0x00;
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/* Set bit for SMP secondary cores boot */
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mmio_clrsetbits_32(L2_RESET_DONE_REG, BS_REG_MAGIC_KEYS_MASK,
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SMP_SEC_CORE_BOOT_REQ);
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boot_core = (mmio_read_32(AGX5_PWRMGR(MPU_BOOTCONFIG)) & 0xC00);
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/* Update the p-channel based on cpu id */
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pch_cpu = 1 << cpu_id;
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if (boot_core == 0x00) {
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/* Update reset vector to 0x00 */
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mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU2,
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(uint64_t) plat_secondary_cpus_bl31_entry >> 2);
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} else {
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/* Update reset vector to 0x00 */
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mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU0,
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(uint64_t) plat_secondary_cpus_bl31_entry >> 2);
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}
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/* Update reset vector to 0x00 */
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mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU1, (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
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mmio_write_64(RSTMGR_CPUxRESETBASELOW_CPU3, (uint64_t) plat_secondary_cpus_bl31_entry >> 2);
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/* On all cores - temporary */
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pchctlr_old = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR));
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pchctlr_new = pchctlr_old | (pch_cpu<<1);
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mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pchctlr_new);
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/* We will only release the target secondary CPUs */
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/* Bit mask for each CPU BIT0-3 */
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mmio_write_32(RSTMGR_CPUSTRELEASE_CPUx, pch_cpu);
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}
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void bl31_plat_set_secondary_cpu_off(void)
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{
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unsigned int pch_cpu = 0x00;
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unsigned int pch_cpu_off = 0x00;
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unsigned int cpu_id = plat_my_core_pos();
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pch_cpu_off = 1 << cpu_id;
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pch_cpu = mmio_read_32(AGX5_PWRMGR(MPU_PCHCTLR));
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pch_cpu = pch_cpu & ~(pch_cpu_off << 1);
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mmio_write_32(AGX5_PWRMGR(MPU_PCHCTLR), pch_cpu);
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}
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void bl31_plat_enable_mmu(uint32_t flags)
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{
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/* TODO: Enable mmu when needed */
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}
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