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765ed9fc55
Define Qemu AArch32 implementation for some platform functions (core position, secondary boot cores, crash console). These are derived from the AArch64 implementation. BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is the first executable image after BL2. Support SP_MIN and OP-TEE as BL32: create a sp_min make script target in Qemu, define mapping for IMAGE_BL32 Minor fix Qemu return value type for plat_get_ns_image_entrypoint(). Qemu model for the Cortex-A15 does not support the virtualization extension although the core expects it. To overcome the issue, Qemu ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0. Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform used by the Qemu platform. Qemu Cortex-A15 model integrates a single cluster with up to 4 cores. Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
31 lines
969 B
C
31 lines
969 B
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __QEMU_PRIVATE_H
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#define __QEMU_PRIVATE_H
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#include <sys/types.h>
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void qemu_configure_mmu_secure(unsigned long total_base,
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unsigned long total_size,
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unsigned long ro_start, unsigned long ro_limit,
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unsigned long coh_start, unsigned long coh_limit);
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void qemu_configure_mmu_el1(unsigned long total_base, unsigned long total_size,
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unsigned long ro_start, unsigned long ro_limit,
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unsigned long coh_start, unsigned long coh_limit);
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void qemu_configure_mmu_el3(unsigned long total_base, unsigned long total_size,
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unsigned long ro_start, unsigned long ro_limit,
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unsigned long coh_start, unsigned long coh_limit);
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void plat_qemu_io_setup(void);
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unsigned int plat_qemu_calc_core_pos(u_register_t mpidr);
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int dt_add_psci_node(void *fdt);
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int dt_add_psci_cpu_enable_methods(void *fdt);
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#endif /*__QEMU_PRIVATE_H*/
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