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https://github.com/ARM-software/arm-trusted-firmware.git
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765ed9fc55
Define Qemu AArch32 implementation for some platform functions (core position, secondary boot cores, crash console). These are derived from the AArch64 implementation. BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is the first executable image after BL2. Support SP_MIN and OP-TEE as BL32: create a sp_min make script target in Qemu, define mapping for IMAGE_BL32 Minor fix Qemu return value type for plat_get_ns_image_entrypoint(). Qemu model for the Cortex-A15 does not support the virtualization extension although the core expects it. To overcome the issue, Qemu ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0. Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform used by the Qemu platform. Qemu Cortex-A15 model integrates a single cluster with up to 4 cores. Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
135 lines
3.2 KiB
C
135 lines
3.2 KiB
C
/*
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* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch_helpers.h>
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#include <bl_common.h>
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#include <platform_def.h>
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#include <arm_xlat_tables.h>
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#include "qemu_private.h"
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#define MAP_DEVICE0 MAP_REGION_FLAT(DEVICE0_BASE, \
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DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#ifdef DEVICE1_BASE
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#define MAP_DEVICE1 MAP_REGION_FLAT(DEVICE1_BASE, \
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#endif
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#ifdef DEVICE2_BASE
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#define MAP_DEVICE2 MAP_REGION_FLAT(DEVICE2_BASE, \
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DEVICE2_SIZE, \
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MT_DEVICE | MT_RO | MT_SECURE)
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#endif
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#define MAP_SHARED_RAM MAP_REGION_FLAT(SHARED_RAM_BASE, \
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SHARED_RAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_BL32_MEM MAP_REGION_FLAT(BL32_MEM_BASE, BL32_MEM_SIZE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_NS_DRAM0 MAP_REGION_FLAT(NS_DRAM0_BASE, NS_DRAM0_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_FLASH0 MAP_REGION_FLAT(QEMU_FLASH0_BASE, QEMU_FLASH0_SIZE, \
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MT_MEMORY | MT_RO | MT_SECURE)
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/*
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* Table of regions for various BL stages to map using the MMU.
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* This doesn't include TZRAM as the 'mem_layout' argument passed to
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* arm_configure_mmu_elx() will give the available subset of that,
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*/
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#ifdef IMAGE_BL1
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static const mmap_region_t plat_qemu_mmap[] = {
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MAP_FLASH0,
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MAP_SHARED_RAM,
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MAP_DEVICE0,
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#ifdef MAP_DEVICE1
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MAP_DEVICE1,
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#endif
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#ifdef MAP_DEVICE2
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MAP_DEVICE2,
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#endif
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{0}
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};
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#endif
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#ifdef IMAGE_BL2
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static const mmap_region_t plat_qemu_mmap[] = {
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MAP_FLASH0,
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MAP_SHARED_RAM,
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MAP_DEVICE0,
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#ifdef MAP_DEVICE1
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MAP_DEVICE1,
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#endif
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#ifdef MAP_DEVICE2
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MAP_DEVICE2,
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#endif
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MAP_NS_DRAM0,
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MAP_BL32_MEM,
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{0}
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};
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#endif
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#ifdef IMAGE_BL31
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static const mmap_region_t plat_qemu_mmap[] = {
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MAP_SHARED_RAM,
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MAP_DEVICE0,
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#ifdef MAP_DEVICE1
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MAP_DEVICE1,
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#endif
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MAP_BL32_MEM,
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{0}
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};
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#endif
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#ifdef IMAGE_BL32
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static const mmap_region_t plat_qemu_mmap[] = {
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MAP_SHARED_RAM,
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MAP_DEVICE0,
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#ifdef MAP_DEVICE1
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MAP_DEVICE1,
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#endif
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{0}
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};
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#endif
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/*******************************************************************************
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* Macro generating the code for the function setting up the pagetables as per
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* the platform memory map & initialize the mmu, for the given exception level
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******************************************************************************/
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#define DEFINE_CONFIGURE_MMU_EL(_el) \
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void qemu_configure_mmu_##_el(unsigned long total_base, \
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unsigned long total_size, \
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unsigned long ro_start, \
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unsigned long ro_limit, \
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unsigned long coh_start, \
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unsigned long coh_limit) \
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{ \
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mmap_add_region(total_base, total_base, \
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total_size, \
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MT_MEMORY | MT_RW | MT_SECURE); \
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mmap_add_region(ro_start, ro_start, \
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ro_limit - ro_start, \
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MT_MEMORY | MT_RO | MT_SECURE); \
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mmap_add_region(coh_start, coh_start, \
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coh_limit - coh_start, \
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MT_DEVICE | MT_RW | MT_SECURE); \
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mmap_add(plat_qemu_mmap); \
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init_xlat_tables(); \
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\
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enable_mmu_##_el(0); \
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}
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/* Define EL1 and EL3 variants of the function initialising the MMU */
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#ifdef AARCH32
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DEFINE_CONFIGURE_MMU_EL(secure)
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#else
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DEFINE_CONFIGURE_MMU_EL(el1)
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DEFINE_CONFIGURE_MMU_EL(el3)
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#endif
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