Jayanth Dodderi Chidanand 59b7c0a03f feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT ... * Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default for few cores and they need context entries for saving and restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times. * This prevents the mechanism of decoupling EL1 and EL2 registers, as EL3 firmware shouldn't be handling both simultaneously. * Depending on the build configuration either EL1 or EL2 context structures need to included, which would result in saving a good amount of context memory. * In order to achieve this it's essential to have explicit context entries for registers supporting "ERRATA_SPECULATIVE_AT". * This patch adds two context entries under "errata_speculative_at" structure to assist this errata and thereby allows decoupling EL1 and EL2 context structures. Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>		2024-07-26 15:36:31 +01:00
..
drtm	feat(drtm): update references to DRTM beta0	2024-03-05 14:17:15 -06:00
errata_abi	chore(errata-abi): minor variable rename	2024-05-30 10:39:24 -05:00
rmmd	Merge changes from topic "makefile-cleanup" into integration	2024-05-07 18:39:53 +02:00
sdei	refactor(sdei): use common create_spsr() in SDEI library	2024-03-07 11:35:49 -06:00
spm	feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT	2024-07-26 15:36:31 +01:00
spmd	refactor(spmd): move plat_my_core_pos calls	2024-07-09 15:23:34 +02:00
trng	refactor(trng): discarding the used entropy bits	2022-11-14 10:08:56 +00:00
pci_svc.c	SMCCC/PCI: Handle std svc boilerplate	2021-05-25 14:49:08 +02:00
std_svc_setup.c	feat(errata_abi): errata management firmware interface	2023-05-05 13:23:10 -05:00