Jayanth Dodderi Chidanand 59b7c0a03f feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT ... * Currently, "ERRATA_SPECUALTIVE_AT" errata is enabled by default for few cores and they need context entries for saving and restoring EL1 regs "SCTLR_EL1 and TCR_EL1" registers at all times. * This prevents the mechanism of decoupling EL1 and EL2 registers, as EL3 firmware shouldn't be handling both simultaneously. * Depending on the build configuration either EL1 or EL2 context structures need to included, which would result in saving a good amount of context memory. * In order to achieve this it's essential to have explicit context entries for registers supporting "ERRATA_SPECULATIVE_AT". * This patch adds two context entries under "errata_speculative_at" structure to assist this errata and thereby allows decoupling EL1 and EL2 context structures. Change-Id: Ia50626eea8fb64899a2e2d81622adbe07fe77d65 Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com>		2024-07-26 15:36:31 +01:00
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aarch32	refactor(cpufeat): add macro to simplify is_feat_xx_present	2024-05-02 12:16:16 -05:00
aarch64	feat(cm): add explicit context entries for ERRATA_SPECULATIVE_AT	2024-07-26 15:36:31 +01:00
cpu_data_array.c	chore: update to use Arm word across TF-A	2023-08-08 15:12:30 +01:00