Igor Podgainõi 58fadd62be fix: add support for 128-bit sysregs to EL3 crash handler ... The following changes have been made: * Add new sysreg definitions and ASM macro is_feat_sysreg128_present_asm * Add registers TTBR0_EL2 and VTTBR_EL2 to EL3 crash handler output * Use MRRS instead of MRS for registers TTBR0_EL1, TTBR0_EL2, TTBR1_EL1, VTTBR_EL2 and PAR_EL1 Change-Id: I0e20b2c35251f3afba2df794c1f8bc0c46c197ff Signed-off-by: Igor Podgainõi <igor.podgainoi@arm.com>		2025-02-05 21:19:15 +01:00
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aarch64	fix: add support for 128-bit sysregs to EL3 crash handler	2025-02-05 21:19:15 +01:00
bl31.ld.S	build(bl31): support separated memory for RW DATA	2024-11-05 17:24:41 +08:00
bl31.mk	feat(fpmr): disable FPMR trap	2024-12-12 10:03:23 -06:00
bl31_context_mgmt.c	feat(rme): add context management changes for FEAT_RME	2021-10-05 18:41:35 +02:00
bl31_main.c	Merge changes from topic "early_console" into integration	2024-05-08 23:12:11 +02:00
bl31_traps.c	docs: review Undefined Injection for 2.12 release	2024-11-14 18:30:02 +02:00
ehf.c	fix(gic600): workaround for Part 1 of GIC600 erratum 2384374	2024-03-06 14:16:35 -06:00
interrupt_mgmt.c	fix(misra): fix MISRA defects	2024-03-07 09:38:27 -06:00