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https://github.com/ARM-software/arm-trusted-firmware.git
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ca661a0092
This flag warns if anything is declared more than once in the same scope, even in cases where multiple declaration is valid and changes nothing. Consequently, this patch also fixes the issues reported by this flag. Consider the following two lines of code from two different source files(bl_common.h and bl31_plat_setup.c): IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE); IMPORT_SYM(unsigned long, __RO_START__, BL2_RO_BASE); The IMPORT_SYM macro which actually imports a linker symbol as a C expression. The macro defines the __RO_START__ as an extern variable twice, one for each instance. __RO_START__ symbol is defined by the linker script to mark the start of the Read-Only area of the memory map. Essentially, the platform code redefines the linker symbol with a different (relevant) name rather than using the standard symbol. A simple solution to fix this issue in the platform code for redundant declarations warning is to remove the second IMPORT_SYM and replace it with following assignment static const unsigned long BL2_RO_BASE = BL_CODE_BASE; Change-Id: If4835d1ee462d52b75e5afd2a59b64828707c5aa Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
173 lines
4.2 KiB
C
173 lines
4.2 KiB
C
/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <drivers/nand.h>
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#include <drivers/raw_nand.h>
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#include <drivers/spi_nand.h>
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#include <drivers/spi_nor.h>
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#include <lib/utils.h>
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#include <plat/common/platform.h>
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#define SZ_512 0x200U
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#define SZ_64M 0x4000000U
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#if STM32MP_RAW_NAND || STM32MP_SPI_NAND
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static int get_data_from_otp(struct nand_device *nand_dev, bool is_slc)
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{
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int result;
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uint32_t nand_param;
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/* Check if NAND parameters are stored in OTP */
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result = bsec_shadow_read_otp(&nand_param, NAND_OTP);
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if (result != BSEC_OK) {
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ERROR("BSEC: NAND_OTP Error %i\n", result);
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return -EACCES;
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}
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if (nand_param == 0U) {
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return 0;
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}
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if ((nand_param & NAND_PARAM_STORED_IN_OTP) == 0U) {
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goto ecc;
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}
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/* NAND parameter shall be read from OTP */
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if ((nand_param & NAND_WIDTH_MASK) != 0U) {
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nand_dev->buswidth = NAND_BUS_WIDTH_16;
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} else {
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nand_dev->buswidth = NAND_BUS_WIDTH_8;
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}
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switch ((nand_param & NAND_PAGE_SIZE_MASK) >> NAND_PAGE_SIZE_SHIFT) {
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case NAND_PAGE_SIZE_2K:
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nand_dev->page_size = 0x800U;
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break;
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case NAND_PAGE_SIZE_4K:
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nand_dev->page_size = 0x1000U;
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break;
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case NAND_PAGE_SIZE_8K:
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nand_dev->page_size = 0x2000U;
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break;
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default:
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ERROR("Cannot read NAND page size\n");
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return -EINVAL;
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}
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switch ((nand_param & NAND_BLOCK_SIZE_MASK) >> NAND_BLOCK_SIZE_SHIFT) {
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case NAND_BLOCK_SIZE_64_PAGES:
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nand_dev->block_size = 64U * nand_dev->page_size;
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break;
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case NAND_BLOCK_SIZE_128_PAGES:
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nand_dev->block_size = 128U * nand_dev->page_size;
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break;
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case NAND_BLOCK_SIZE_256_PAGES:
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nand_dev->block_size = 256U * nand_dev->page_size;
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break;
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default:
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ERROR("Cannot read NAND block size\n");
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return -EINVAL;
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}
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nand_dev->size = ((nand_param & NAND_BLOCK_NB_MASK) >>
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NAND_BLOCK_NB_SHIFT) *
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NAND_BLOCK_NB_UNIT * nand_dev->block_size;
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ecc:
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if (is_slc) {
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switch ((nand_param & NAND_ECC_BIT_NB_MASK) >>
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NAND_ECC_BIT_NB_SHIFT) {
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case NAND_ECC_BIT_NB_1_BITS:
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nand_dev->ecc.max_bit_corr = 1U;
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break;
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case NAND_ECC_BIT_NB_4_BITS:
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nand_dev->ecc.max_bit_corr = 4U;
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break;
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case NAND_ECC_BIT_NB_8_BITS:
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nand_dev->ecc.max_bit_corr = 8U;
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break;
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case NAND_ECC_ON_DIE:
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nand_dev->ecc.mode = NAND_ECC_ONDIE;
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break;
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default:
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if (nand_dev->ecc.max_bit_corr == 0U) {
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ERROR("No valid eccbit number\n");
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return -EINVAL;
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}
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}
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} else {
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/* Selected multiple plane NAND */
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if ((nand_param & NAND_PLANE_BIT_NB_MASK) != 0U) {
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nand_dev->nb_planes = 2U;
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} else {
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nand_dev->nb_planes = 1U;
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}
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}
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VERBOSE("OTP: Block %i Page %i Size %lli\n", nand_dev->block_size,
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nand_dev->page_size, nand_dev->size);
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return 0;
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}
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#endif /* STM32MP_RAW_NAND || STM32MP_SPI_NAND */
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#if STM32MP_RAW_NAND
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int plat_get_raw_nand_data(struct rawnand_device *device)
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{
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device->nand_dev->ecc.mode = NAND_ECC_HW;
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device->nand_dev->ecc.size = SZ_512;
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return get_data_from_otp(device->nand_dev, true);
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}
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#endif
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#if STM32MP_SPI_NAND
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int plat_get_spi_nand_data(struct spinand_device *device)
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{
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zeromem(&device->spi_read_cache_op, sizeof(struct spi_mem_op));
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device->spi_read_cache_op.cmd.opcode = SPI_NAND_OP_READ_FROM_CACHE_4X;
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device->spi_read_cache_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.addr.nbytes = 2U;
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device->spi_read_cache_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.dummy.nbytes = 1U;
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device->spi_read_cache_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->spi_read_cache_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE;
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device->spi_read_cache_op.data.dir = SPI_MEM_DATA_IN;
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return get_data_from_otp(device->nand_dev, false);
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}
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#endif
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#if STM32MP_SPI_NOR
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int plat_get_nor_data(struct nor_device *device)
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{
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device->size = SZ_64M;
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zeromem(&device->read_op, sizeof(struct spi_mem_op));
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device->read_op.cmd.opcode = SPI_NOR_OP_READ_1_1_4;
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device->read_op.cmd.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->read_op.addr.nbytes = 3U;
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device->read_op.addr.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->read_op.dummy.nbytes = 1U;
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device->read_op.dummy.buswidth = SPI_MEM_BUSWIDTH_1_LINE;
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device->read_op.data.buswidth = SPI_MEM_BUSWIDTH_4_LINE;
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device->read_op.data.dir = SPI_MEM_DATA_IN;
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return 0;
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}
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#endif
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