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https://github.com/ARM-software/arm-trusted-firmware.git
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84686ba347
A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.
The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.
PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.
BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.
Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: Yann Gautier <yann.gautier@st.com>
167 lines
3 KiB
C
167 lines
3 KiB
C
/*
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* Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <errno.h>
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#include <platform_def.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/st/stm32mp_clkfunc.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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uintptr_t plat_get_ns_image_entrypoint(void)
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{
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return BL33_BASE;
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}
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unsigned int plat_get_syscnt_freq2(void)
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{
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return read_cntfrq_el0();
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}
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static uintptr_t boot_ctx_address;
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void stm32mp_save_boot_ctx_address(uintptr_t address)
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{
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boot_ctx_address = address;
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}
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uintptr_t stm32mp_get_boot_ctx_address(void)
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{
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return boot_ctx_address;
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}
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uintptr_t stm32mp_ddrctrl_base(void)
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{
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static uintptr_t ddrctrl_base;
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if (ddrctrl_base == 0) {
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ddrctrl_base = dt_get_ddrctrl_base();
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assert(ddrctrl_base == DDRCTRL_BASE);
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}
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return ddrctrl_base;
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}
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uintptr_t stm32mp_ddrphyc_base(void)
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{
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static uintptr_t ddrphyc_base;
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if (ddrphyc_base == 0) {
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ddrphyc_base = dt_get_ddrphyc_base();
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assert(ddrphyc_base == DDRPHYC_BASE);
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}
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return ddrphyc_base;
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}
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uintptr_t stm32mp_pwr_base(void)
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{
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static uintptr_t pwr_base;
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if (pwr_base == 0) {
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pwr_base = dt_get_pwr_base();
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assert(pwr_base == PWR_BASE);
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}
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return pwr_base;
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}
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uintptr_t stm32mp_rcc_base(void)
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{
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static uintptr_t rcc_base;
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if (rcc_base == 0) {
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rcc_base = fdt_rcc_read_addr();
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assert(rcc_base == RCC_BASE);
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}
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return rcc_base;
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}
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bool stm32mp_lock_available(void)
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{
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const uint32_t c_m_bits = SCTLR_M_BIT | SCTLR_C_BIT;
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/* The spinlocks are used only when MMU and data cache are enabled */
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return (read_sctlr() & c_m_bits) == c_m_bits;
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}
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uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return GPIOZ_BASE;
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}
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assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
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return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
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}
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uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
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{
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if (bank == GPIO_BANK_Z) {
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return 0;
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}
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assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
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return bank * GPIO_BANK_OFFSET;
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}
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int stm32mp_check_header(boot_api_image_header_t *header, uintptr_t buffer)
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{
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uint32_t i;
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uint32_t img_checksum = 0U;
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/*
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* Check header/payload validity:
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* - Header magic
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* - Header version
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* - Payload checksum
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*/
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if (header->magic != BOOT_API_IMAGE_HEADER_MAGIC_NB) {
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ERROR("Header magic\n");
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return -EINVAL;
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}
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if (header->header_version != BOOT_API_HEADER_VERSION) {
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ERROR("Header version\n");
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return -EINVAL;
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}
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for (i = 0U; i < header->image_length; i++) {
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img_checksum += *(uint8_t *)(buffer + i);
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}
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if (header->payload_checksum != img_checksum) {
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ERROR("Checksum: 0x%x (awaited: 0x%x)\n", img_checksum,
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header->payload_checksum);
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return -EINVAL;
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}
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return 0;
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}
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int stm32mp_map_ddr_non_cacheable(void)
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{
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return mmap_add_dynamic_region(STM32MP_DDR_BASE, STM32MP_DDR_BASE,
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STM32MP_DDR_MAX_SIZE,
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MT_NON_CACHEABLE | MT_RW | MT_NS);
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}
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int stm32mp_unmap_ddr(void)
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{
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return mmap_remove_dynamic_region(STM32MP_DDR_BASE,
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STM32MP_DDR_MAX_SIZE);
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}
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