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84686ba347
A speculative accesses to DDR could be done whereas it was not reachable
and could lead to bus stall.
To correct this the dynamic mapping in MMU is used.
A first mapping is done for DDR tests with MT_NON_CACHEABLE attribute,
once DDR access is setup. It is then unmapped and a new mapping DDR is done
with cacheable attribute (through MT_MEMORY) to speed-up BL33 (or OP-TEE)
load.
The disabling of cache during DDR tests is also removed, as now useless.
A call to new functions stm32mp_{,un}map_ddr_non_cacheable() is done
instead.
PLAT_XLAT_TABLES_DYNAMIC is activated globally as used in BL2 and BL32.
BL33 max size is also updated to take into account the secure and shared
memory areas. Those are used in OP-TEE case.
Change-Id: I22c48b4a48255ee264991c34ecbb15bfe87e67c3
Signed-off-by: Yann Gautier <yann.gautier@st.com>
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| .. | ||
| allwinner | ||
| amlogic | ||
| arm | ||
| auth | ||
| cadence/uart/aarch64 | ||
| cfi/v2m | ||
| console | ||
| coreboot/cbmem_console/aarch64 | ||
| delay_timer | ||
| gpio | ||
| imx | ||
| intel/soc/stratix10/io | ||
| io | ||
| marvell | ||
| mentor/i2c | ||
| mmc | ||
| mtd | ||
| partition | ||
| renesas/rcar | ||
| rpi3 | ||
| st | ||
| synopsys | ||
| ti/uart | ||
| ufs | ||