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https://github.com/ARM-software/arm-trusted-firmware.git
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5724481fdd
MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
190 lines
5.1 KiB
C
190 lines
5.1 KiB
C
/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef __PLATFORM_DEF_H__
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#define __PLATFORM_DEF_H__
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#include <arch.h>
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#include "../hikey_def.h"
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/* Special value used to verify platform parameters from BL2 to BL3-1 */
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#define HIKEY_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
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/*
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* Generic platform constants
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*/
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/* Size of cacheable stacks */
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#define PLATFORM_STACK_SIZE 0x800
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#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
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#define PLATFORM_CACHE_LINE_SIZE 64
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#define PLATFORM_CLUSTER_COUNT 2
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#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
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#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
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PLATFORM_CORE_COUNT_PER_CLUSTER)
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#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
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#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
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PLATFORM_CLUSTER_COUNT + 1)
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#define PLAT_MAX_RET_STATE 1
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#define PLAT_MAX_OFF_STATE 2
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#define MAX_IO_DEVICES 3
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#define MAX_IO_HANDLES 4
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/* eMMC RPMB and eMMC User Data */
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#define MAX_IO_BLOCK_DEVICES 2
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/* GIC related constants (no GICR in GIC-400) */
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#define PLAT_ARM_GICD_BASE 0xF6801000
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#define PLAT_ARM_GICC_BASE 0xF6802000
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#define PLAT_ARM_GICH_BASE 0xF6804000
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#define PLAT_ARM_GICV_BASE 0xF6806000
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/*
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* Platform memory map related constants
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*/
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/*
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* BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
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*/
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#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
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#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
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#define BL1_XG2RAM0_OFFSET 0x1000
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/*
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* BL1 specific defines.
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*
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* Both loader and BL1_RO region stay in SRAM since they are used to simulate
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* ROM.
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* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
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*
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* ++++++++++ 0xF980_0000
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* + loader +
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* ++++++++++ 0xF980_1000
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* + BL1_RO +
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* ++++++++++ 0xF981_0000
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* + BL1_RW +
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* ++++++++++ 0xF989_8000
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*/
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#define BL1_RO_BASE (XG2RAM0_BASE + BL1_XG2RAM0_OFFSET)
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#define BL1_RO_LIMIT (XG2RAM0_BASE + 0x10000)
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#define BL1_RW_BASE (BL1_RO_LIMIT) /* 0xf981_0000 */
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#define BL1_RW_SIZE (0x00088000)
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#define BL1_RW_LIMIT (0xF9898000)
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/*
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* BL2 specific defines.
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*/
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#define BL2_BASE (BL1_RW_BASE + 0x8000) /* 0xf981_8000 */
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#define BL2_LIMIT (BL2_BASE + 0x40000)
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/*
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* SCP_BL2 specific defines.
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* In HiKey, SCP_BL2 means MCU firmware. It's loaded into the temporary buffer
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* at 0x0100_0000. Then BL2 will parse the sections and loaded them into
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* predefined separated buffers.
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*/
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#define SCP_BL2_BASE (DDR_BASE + 0x01000000)
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#define SCP_BL2_LIMIT (SCP_BL2_BASE + 0x00100000)
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#define SCP_BL2_SIZE (SCP_BL2_LIMIT - SCP_BL2_BASE)
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/*
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* BL31 specific defines.
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*/
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#define BL31_BASE BL2_LIMIT /* 0xf985_8000 */
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#define BL31_LIMIT 0xF9898000
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/*
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* BL3-2 specific defines.
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*/
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/*
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* The TSP currently executes from TZC secured area of DRAM or SRAM.
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*/
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#define BL32_SRAM_BASE BL31_LIMIT
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#define BL32_SRAM_LIMIT (BL31_LIMIT+0x80000) /* 512K */
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#define BL32_DRAM_BASE DDR_SEC_BASE
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#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
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#if LOAD_IMAGE_V2
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#ifdef SPD_opteed
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/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
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#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
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#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
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#endif
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#endif
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#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
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#define BL32_BASE BL32_DRAM_BASE
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#define BL32_LIMIT BL32_DRAM_LIMIT
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#elif (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_SRAM_ID)
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#define TSP_SEC_MEM_BASE BL32_SRAM_BASE
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#define TSP_SEC_MEM_SIZE (BL32_SRAM_LIMIT - BL32_SRAM_BASE)
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#define BL32_BASE BL32_SRAM_BASE
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#define BL32_LIMIT BL32_SRAM_LIMIT
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#else
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#error "Currently unsupported HIKEY_TSP_LOCATION_ID value"
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#endif
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/* BL32 is mandatory in AArch32 */
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#ifndef AARCH32
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#ifdef SPD_none
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#undef BL32_BASE
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#endif /* SPD_none */
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#endif
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#define NS_BL1U_BASE (BL2_BASE)
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#define NS_BL1U_SIZE (0x00010000)
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#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
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/*
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* Platform specific page table and MMU setup constants
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*/
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#define ADDR_SPACE_SIZE (1ULL << 32)
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#if defined(IMAGE_BL1) || defined(IMAGE_BL32)
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#define MAX_XLAT_TABLES 3
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#endif
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#ifdef IMAGE_BL31
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#define MAX_XLAT_TABLES 4
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#endif
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#ifdef IMAGE_BL2
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#if LOAD_IMAGE_V2
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#ifdef SPD_opteed
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#define MAX_XLAT_TABLES 4
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#else
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#define MAX_XLAT_TABLES 3
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#endif
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#else
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#define MAX_XLAT_TABLES 3
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#endif
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#endif
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#define MAX_MMAP_REGIONS 16
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#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
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/*
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* Declarations and constants to access the mailboxes safely. Each mailbox is
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* aligned on the biggest cache line size in the platform. This is known only
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* to the platform as it might have a combination of integrated and external
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* caches. Such alignment ensures that two maiboxes do not sit on the same cache
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* line at any cache level. They could belong to different cpus/clusters &
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* get written while being protected by different locks causing corruption of
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* a valid mailbox address.
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*/
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#define CACHE_WRITEBACK_SHIFT 6
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#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
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#endif /* __PLATFORM_DEF_H__ */
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