mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-24 05:54:08 +00:00
b1063d955b
From version 4.0 onwards, the ARM64 Linux kernel expects the device
tree to indicate the cache hierarchy. Failing to provide this
information results in the following warning message to be printed by
the kernel:
`Unable to detect cache hierarchy from DT for CPU x`
All the FVP device trees provided in the TF source tree have been
modified to add this information.
Fixes ARM-software/tf-issues#325
Change-Id: I0ff888992e602b81a0fe1744a86151d625727511
331 lines
7.8 KiB
Text
331 lines
7.8 KiB
Text
/*
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* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/dts-v1/;
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/memreserve/ 0x80000000 0x00010000;
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/ {
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};
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/ {
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model = "FVP Base";
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compatible = "arm,vfp-base", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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};
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psci {
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compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
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method = "smc";
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cpu_suspend = <0xc4000001>;
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cpu_off = <0x84000002>;
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cpu_on = <0xc4000003>;
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sys_poweroff = <0x84000008>;
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sys_reset = <0x84000009>;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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idle-states {
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entry-method = "arm,psci";
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CPU_SLEEP_0: cpu-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x0010000>;
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entry-latency-us = <40>;
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exit-latency-us = <100>;
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min-residency-us = <150>;
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};
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CLUSTER_SLEEP_0: cluster-sleep-0 {
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compatible = "arm,idle-state";
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local-timer-stop;
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arm,psci-suspend-param = <0x1010000>;
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entry-latency-us = <500>;
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exit-latency-us = <1000>;
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min-residency-us = <2500>;
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};
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};
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CPU0:cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU1:cpu@1 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU2:cpu@2 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU3:cpu@3 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU4:cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU5:cpu@101 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x101>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU6:cpu@102 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x102>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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CPU7:cpu@103 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x103>;
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enable-method = "psci";
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cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
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next-level-cache = <&L2_0>;
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};
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L2_0: l2-cache0 {
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compatible = "cache";
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};
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0 0x7F000000>,
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<0x00000008 0x80000000 0 0x80000000>;
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};
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gic: interrupt-controller@2f000000 {
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compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x0 0x2f000000 0 0x10000>,
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<0x0 0x2c000000 0 0x2000>,
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<0x0 0x2c010000 0 0x2000>,
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<0x0 0x2c02F000 0 0x2000>;
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interrupts = <1 9 0xf04>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <1 13 0xff01>,
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<1 14 0xff01>,
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<1 11 0xff01>,
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<1 10 0xff01>;
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clock-frequency = <100000000>;
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};
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timer@2a810000 {
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compatible = "arm,armv7-timer-mem";
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reg = <0x0 0x2a810000 0x0 0x10000>;
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clock-frequency = <100000000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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frame@2a830000 {
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frame-number = <1>;
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interrupts = <0 26 4>;
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reg = <0x0 0x2a830000 0x0 0x10000>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <0 60 4>,
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<0 61 4>,
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<0 62 4>,
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<0 63 4>;
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0 0x08000000 0x04000000>,
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<1 0 0 0x14000000 0x04000000>,
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<2 0 0 0x18000000 0x04000000>,
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<3 0 0 0x1c000000 0x04000000>,
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<4 0 0 0x0c000000 0x04000000>,
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<5 0 0 0x10000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 4>,
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<0 0 1 &gic 0 1 4>,
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<0 0 2 &gic 0 2 4>,
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<0 0 3 &gic 0 3 4>,
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<0 0 4 &gic 0 4 4>,
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<0 0 5 &gic 0 5 4>,
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<0 0 6 &gic 0 6 4>,
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<0 0 7 &gic 0 7 4>,
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<0 0 8 &gic 0 8 4>,
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<0 0 9 &gic 0 9 4>,
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<0 0 10 &gic 0 10 4>,
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<0 0 11 &gic 0 11 4>,
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<0 0 12 &gic 0 12 4>,
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<0 0 13 &gic 0 13 4>,
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<0 0 14 &gic 0 14 4>,
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<0 0 15 &gic 0 15 4>,
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<0 0 16 &gic 0 16 4>,
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<0 0 17 &gic 0 17 4>,
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<0 0 18 &gic 0 18 4>,
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<0 0 19 &gic 0 19 4>,
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<0 0 20 &gic 0 20 4>,
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<0 0 21 &gic 0 21 4>,
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<0 0 22 &gic 0 22 4>,
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<0 0 23 &gic 0 23 4>,
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<0 0 24 &gic 0 24 4>,
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<0 0 25 &gic 0 25 4>,
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<0 0 26 &gic 0 26 4>,
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<0 0 27 &gic 0 27 4>,
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<0 0 28 &gic 0 28 4>,
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<0 0 29 &gic 0 29 4>,
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<0 0 30 &gic 0 30 4>,
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<0 0 31 &gic 0 31 4>,
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<0 0 32 &gic 0 32 4>,
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<0 0 33 &gic 0 33 4>,
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<0 0 34 &gic 0 34 4>,
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<0 0 35 &gic 0 35 4>,
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<0 0 36 &gic 0 36 4>,
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<0 0 37 &gic 0 37 4>,
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<0 0 38 &gic 0 38 4>,
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<0 0 39 &gic 0 39 4>,
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<0 0 40 &gic 0 40 4>,
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<0 0 41 &gic 0 41 4>,
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<0 0 42 &gic 0 42 4>;
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/include/ "rtsm_ve-motherboard.dtsi"
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};
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panels {
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panel@0 {
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compatible = "panel";
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mode = "XVGA";
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refresh = <60>;
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xres = <1024>;
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yres = <768>;
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pixclock = <15748>;
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left_margin = <152>;
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right_margin = <48>;
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upper_margin = <23>;
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lower_margin = <3>;
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hsync_len = <104>;
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vsync_len = <4>;
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sync = <0>;
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vmode = "FB_VMODE_NONINTERLACED";
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tim2 = "TIM2_BCD", "TIM2_IPC";
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cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
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caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
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bpp = <16>;
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};
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};
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};
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