Soby Mathew 5541bb3f61 Optimize Cortex-A57 cluster power down sequence on Juno ... This patch optimizes the Cortex-A57 cluster power down sequence by not flushing the Level1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. This optimization can be enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build flag. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This patch also renames the cpu-errata-workarounds.md to cpu-specific-build-macros.md as this facilitates documentation of both CPU Specific errata and CPU Specific Optimization build macros. Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480		2014-10-29 17:39:59 +00:00
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diagrams	Document design of the Interrupt Mangement Framework	2014-06-03 18:42:14 +01:00
change-log.md	Documentation for version 1.0	2014-08-28 14:24:54 +01:00
cpu-specific-build-macros.md	Optimize Cortex-A57 cluster power down sequence on Juno	2014-10-29 17:39:59 +00:00
firmware-design.md	Optimize Cortex-A57 cluster power down sequence on Juno	2014-10-29 17:39:59 +00:00
interrupt-framework-design.md	Miscellaneous documentation fixes	2014-08-27 19:13:56 +01:00
optee-dispatcher.md	Add opteed based on tspd	2014-09-16 11:51:54 -07:00
porting-guide.md	Add support for specifying pre-built BL binaries in Makefile	2014-09-16 17:55:19 +01:00
rt-svc-writers-guide.md	Implement ARM Standard Service	2014-03-20 11:16:23 +00:00
user-guide.md	Merge pull request #217 from jcastillo-arm/jc/tf-issues/257	2014-10-28 12:25:51 +00:00