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5541bb3f61
This patch optimizes the Cortex-A57 cluster power down sequence by not flushing the Level1 data cache. The L1 data cache and the L2 unified cache are inclusive. A flush of the L2 by set/way flushes any dirty lines from the L1 as well. This is a known safe deviation from the Cortex-A57 TRM defined power down sequence. This optimization can be enabled by the platform through the 'SKIP_A57_L1_FLUSH_PWR_DWN' build flag. Each Cortex-A57 based platform must make its own decision on whether to use the optimization. This patch also renames the cpu-errata-workarounds.md to cpu-specific-build-macros.md as this facilitates documentation of both CPU Specific errata and CPU Specific Optimization build macros. Change-Id: I299b9fe79e9a7e08e8a0dffb7d345f9a00a71480
57 lines
2.4 KiB
Makefile
57 lines
2.4 KiB
Makefile
#
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# Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are met:
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#
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# Redistributions of source code must retain the above copyright notice, this
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# list of conditions and the following disclaimer.
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#
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# Redistributions in binary form must reproduce the above copyright notice,
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# this list of conditions and the following disclaimer in the documentation
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# and/or other materials provided with the distribution.
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#
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# Neither the name of ARM nor the names of its contributors may be used
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# to endorse or promote products derived from this software without specific
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# prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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# POSSIBILITY OF SUCH DAMAGE.
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#
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# Cortex A57 specific optimisation to skip L1 cache flush when
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# cluster is powered down.
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SKIP_A57_L1_FLUSH_PWR_DWN ?=0
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# Process SKIP_A57_L1_FLUSH_PWR_DWN flag
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$(eval $(call assert_boolean,SKIP_A57_L1_FLUSH_PWR_DWN))
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$(eval $(call add_define,SKIP_A57_L1_FLUSH_PWR_DWN))
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# CPU Errata Build flags. These should be enabled by the
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# platform if the errata needs to be applied.
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# Flag to apply errata 806969 during reset. This errata applies only to
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# revision r0p0 of the Cortex A57 cpu.
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ERRATA_A57_806969 ?=0
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# Flag to apply errata 813420 during reset. This errata applies only to
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# revision r0p0 of the Cortex A57 cpu.
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ERRATA_A57_813420 ?=0
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# Process ERRATA_A57_806969 flag
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$(eval $(call assert_boolean,ERRATA_A57_806969))
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$(eval $(call add_define,ERRATA_A57_806969))
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# Process ERRATA_A57_813420 flag
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$(eval $(call assert_boolean,ERRATA_A57_813420))
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$(eval $(call add_define,ERRATA_A57_813420))
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