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6744d07d94
RPi 5 has newer Armv8.2 cores where the MT bit is set to indicate that the lowest affinity level represents a thread, but there is only one thread per core. To deal with this, simply right shift MPIDR by one affinity level to get the cluster and core IDs back into Aff1 and Aff0 as expected. Change-Id: I2bafba38f82fd9a6ef6f2fdf2c089b754279a6de Signed-off-by: Mario Bălănică <mariobalanica02@gmail.com>
267 lines
7.3 KiB
ArmAsm
267 lines
7.3 KiB
ArmAsm
/*
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* Copyright (c) 2015-2024, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <platform_def.h>
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#include <cortex_a72.h>
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.globl plat_crash_console_flush
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl platform_mem_init
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.globl plat_get_my_entrypoint
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_reset_handler
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.globl plat_rpi3_calc_core_pos
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.globl plat_secondary_cold_boot_setup
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.globl plat_rpi_get_model
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void)
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*
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* This function uses the plat_rpi3_calc_core_pos()
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* definition to get the index of the calling CPU.
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*
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* When MT is set, lowest affinity represents the thread ID.
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* Since we only support one thread per core, discard this field
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* so cluster and core IDs go back into Aff1 and Aff0 respectively.
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* The upper bits are also affected, but plat_rpi3_calc_core_pos()
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* does not use them.
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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tst x0, #MPIDR_MT_MASK
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lsr x1, x0, #MPIDR_AFFINITY_BITS
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csel x0, x1, x0, ne
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b plat_rpi3_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_rpi3_calc_core_pos(u_register_t mpidr);
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*
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* CorePos = (ClusterId * 4) + CoreId
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* -----------------------------------------------------
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*/
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func plat_rpi3_calc_core_pos
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and x1, x0, #MPIDR_CPU_MASK
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and x0, x0, #MPIDR_CLUSTER_MASK
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add x0, x1, x0, LSR #6
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ret
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endfunc plat_rpi3_calc_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary (void);
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*
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* Find out whether the current cpu is the primary
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* cpu.
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #RPI_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* -----------------------------------------------------
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* void plat_wait_for_warm_boot (void);
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*
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* This function performs any platform specific actions
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* needed for a CPU to be put into holding pen to wait
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* for a warm boot request.
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* The function will never return.
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* -----------------------------------------------------
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*/
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func plat_wait_for_warm_boot
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/*
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* Calculate address of our hold entry.
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* As the function will never return, there is no need to save LR.
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*/
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bl plat_my_core_pos
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lsl x0, x0, #3
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mov_imm x2, PLAT_RPI3_TM_HOLD_BASE
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add x0, x0, x2
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/*
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* This code runs way before requesting the warmboot of this core,
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* so it is possible to clear the mailbox before getting a request
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* to boot.
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*/
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mov x1, PLAT_RPI3_TM_HOLD_STATE_WAIT
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str x1,[x0]
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/* Wait until we have a go */
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poll_mailbox:
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wfe
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ldr x1, [x0]
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cmp x1, PLAT_RPI3_TM_HOLD_STATE_GO
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bne poll_mailbox
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/* Jump to the provided entrypoint */
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mov_imm x0, PLAT_RPI3_TM_ENTRYPOINT
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ldr x1, [x0]
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br x1
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endfunc plat_wait_for_warm_boot
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/* -----------------------------------------------------
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* void plat_secondary_cold_boot_setup (void);
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*
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* This function performs any platform specific actions
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* needed for a secondary cpu after a cold reset e.g
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* mark the cpu's presence, mechanism to place it in a
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* holding pen etc.
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* -----------------------------------------------------
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*/
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func plat_secondary_cold_boot_setup
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b plat_wait_for_warm_boot
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endfunc plat_secondary_cold_boot_setup
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/* ---------------------------------------------------------------------
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* uintptr_t plat_get_my_entrypoint (void);
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*
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* Main job of this routine is to distinguish between a cold and a warm
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* boot.
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*
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* This functions returns:
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* - 0 for a cold boot.
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* - Any other value for a warm boot.
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* ---------------------------------------------------------------------
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*/
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func plat_get_my_entrypoint
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mov x1, x30
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bl plat_is_my_cpu_primary
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/*
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* Secondaries always cold boot.
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*/
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cbz w0, 1f
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/*
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* Primaries warm boot if they are requested
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* to power off.
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*/
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mov_imm x0, PLAT_RPI3_TM_HOLD_BASE
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ldr x0, [x0]
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cmp x0, PLAT_RPI3_TM_HOLD_STATE_BSP_OFF
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adr x0, plat_wait_for_warm_boot
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csel x0, x0, xzr, eq
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ret x1
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1: mov x0, #0
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ret x1
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endfunc plat_get_my_entrypoint
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/* ---------------------------------------------
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* void platform_mem_init (void);
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*
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* No need to carry out any memory initialization.
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* ---------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* Function to initialize the crash console
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* without a C Runtime to print crash report.
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* Clobber list : x0 - x3
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, PLAT_RPI_CRASH_UART_BASE
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#if PLAT_RPI_CRASH_UART_BASE == PLAT_RPI_PL011_UART_BASE
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mov_imm x1, RPI4_PL011_UART_CLOCK
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mov_imm x2, PLAT_RPI_UART_BAUDRATE
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b console_pl011_core_init
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#else
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mov x1, xzr
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mov x2, xzr
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b console_16550_core_init
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#endif
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Function to print a character on the crash
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* console without a C Runtime.
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, PLAT_RPI_CRASH_UART_BASE
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#if PLAT_RPI_CRASH_UART_BASE == PLAT_RPI_PL011_UART_BASE
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b console_pl011_core_putc
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#else
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b console_16550_core_putc
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#endif
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* void plat_crash_console_flush()
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* Function to force a write of all buffered
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* data that hasn't been output.
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* Out : void.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, PLAT_RPI_CRASH_UART_BASE
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#if PLAT_RPI_CRASH_UART_BASE == PLAT_RPI_PL011_UART_BASE
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b console_pl011_core_flush
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#else
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b console_16550_core_flush
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#endif
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endfunc plat_crash_console_flush
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/* ---------------------------------------------
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* int plat_rpi_get_model()
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* Macro to determine whether we are running on
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* a Raspberry Pi 3 or 4. Just checks the MIDR for
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* being either a Cortex-A72 or a Cortex-A53.
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* Out : return 4 if RPi4, 3 otherwise.
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* Clobber list : x0
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* ---------------------------------------------
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*/
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.macro _plat_rpi_get_model
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mrs x0, midr_el1
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and x0, x0, #0xf0 /* Isolate low byte of part number */
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cmp w0, #0x80 /* Cortex-A72 (RPi4) is 0xd08, A53 is 0xd03 */
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mov w0, #3
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csinc w0, w0, w0, ne
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.endm
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func plat_rpi_get_model
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_plat_rpi_get_model
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ret
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endfunc plat_rpi_get_model
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/* ---------------------------------------------
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* void plat_reset_handler(void);
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* ---------------------------------------------
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*/
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func plat_reset_handler
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/* L2 cache setup only needed on RPi4 */
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_plat_rpi_get_model
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cmp w0, #4
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b.ne 1f
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/* ------------------------------------------------
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* Set L2 read/write cache latency:
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* - L2 Data RAM latency: 3 cycles (0b010)
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* - L2 Data RAM setup: 1 cycle (bit 5)
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* ------------------------------------------------
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*/
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mrs x0, CORTEX_A72_L2CTLR_EL1
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mov x1, #0x22
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orr x0, x0, x1
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msr CORTEX_A72_L2CTLR_EL1, x0
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isb
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1:
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ret
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endfunc plat_reset_handler
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