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355ce0a43a
Cortex-X3 erratum 2779509 is a Cat B erratum that applies to all revisions <= r1p1 and is fixed in r1p2. The workaround is to set chicken bit CPUACTLR3_EL1[47], this might have a small impact on power and has negligible impact on performance. SDEN documentation: https://developer.arm.com/documentation/2055130/latest Change-Id: Id92dbae6f1f313b133ffaa018fbf9c078da55d75 Signed-off-by: Sona Mathew <sonarebecca.mathew@arm.com>
56 lines
2.4 KiB
C
56 lines
2.4 KiB
C
/*
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* Copyright (c) 2021-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X3_H
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#define CORTEX_X3_H
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#define CORTEX_X3_MIDR U(0x410FD4E0)
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/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X3_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
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#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
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#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
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/*******************************************************************************
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* CPU Extended Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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#define CORTEX_X3_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(0x9)
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/*******************************************************************************
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* CPU Auxiliary Control register 3 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR3_EL1 S3_0_C15_C1_2
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#define CORTEX_X3_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
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#endif /* CORTEX_X3_H */
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