Harrison Mutai f1cbbd6332 fix(bl1): invalidate SP in data cache during secure SMC ... Invalidate the SP holding `smc_ctx_t` prior to enabling the data cache when handling SMCs from the secure world. Enabling the data cache without doing so results in dirty data either being evicted into main memory, or being used directly from bl1. This corrupted data causes system failure as the SMC handler attempts to use it. Change-Id: I5b7225a6fdd1fcfe34ee054ca46dffea06b84b7d Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>		2022-05-18 09:32:08 +01:00
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aarch32	fix(bl1): invalidate SP in data cache during secure SMC	2022-05-18 09:32:08 +01:00
aarch64	refactor(el3-runtime): add prepare_el3_entry func	2022-01-31 11:27:11 +00:00
tbbr	Coverity: remove unnecessary header file includes	2020-02-04 10:23:51 -06:00
bl1.ld.S	linker_script: move .data section to bl_common.ld.h	2020-04-25 20:09:08 +09:00
bl1.mk	refactor(fvp_r): tidy up platform port [1]	2021-10-06 17:38:06 +01:00
bl1_fwu.c	Fix MISRA C issues in BL1/BL2/BL31	2020-04-03 16:20:59 -05:00
bl1_main.c	refactor(measured-boot): avoid Measured-Boot dependency on Trusted-Boot	2022-01-11 23:06:22 +00:00
bl1_private.h	feat(rme): run BL2 in root world when FEAT_RME is enabled	2021-10-04 21:13:20 +02:00