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1471475516
This patch adds the basic CPU library code to support the Poseidon CPU in TF-A. Poseidon is derived from HunterELP core, an implementation of v9.2 architecture. Currently, Hunter CPU the predecessor to HunterELP, is supported in TF-A. Accordingly the Hunter CPU library code has been as the base and adapted here. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I406b4de156a67132e6a5523370115aaac933f18d
77 lines
2.2 KiB
ArmAsm
77 lines
2.2 KiB
ArmAsm
/*
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* Copyright (c) 2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <neoverse_poseidon.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Neoverse Poseidon must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Neoverse Poseidon supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func neoverse_poseidon_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, NEOVERSE_POSEIDON_CPUPWRCTLR_EL1
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orr x0, x0, #NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr NEOVERSE_POSEIDON_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc neoverse_poseidon_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Neoverse Poseidon. Must follow AAPCS.
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*/
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func neoverse_poseidon_errata_report
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ret
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endfunc neoverse_poseidon_errata_report
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#endif
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func neoverse_poseidon_reset_func
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/* Disable speculative loads */
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msr SSBS, xzr
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isb
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ret
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endfunc neoverse_poseidon_reset_func
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/* ---------------------------------------------
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* This function provides Neoverse-Poseidon specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.neoverse_poseidon_regs, "aS"
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neoverse_poseidon_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func neoverse_poseidon_cpu_reg_dump
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adr x6, neoverse_poseidon_regs
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mrs x8, NEOVERSE_POSEIDON_CPUECTLR_EL1
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ret
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endfunc neoverse_poseidon_cpu_reg_dump
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declare_cpu_ops neoverse_poseidon, NEOVERSE_POSEIDON_MIDR, \
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neoverse_poseidon_reset_func, \
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neoverse_poseidon_core_pwr_dwn
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