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1471475516
This patch adds the basic CPU library code to support the Poseidon CPU in TF-A. Poseidon is derived from HunterELP core, an implementation of v9.2 architecture. Currently, Hunter CPU the predecessor to HunterELP, is supported in TF-A. Accordingly the Hunter CPU library code has been as the base and adapted here. Signed-off-by: Jayanth Dodderi Chidanand <jayanthdodderi.chidanand@arm.com> Change-Id: I406b4de156a67132e6a5523370115aaac933f18d
24 lines
876 B
C
24 lines
876 B
C
/*
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* Copyright (c) 2022, ARM Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_POSEIDON_H
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#define NEOVERSE_POSEIDON_H
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#define NEOVERSE_POSEIDON_MIDR U(0x410FD830)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_POSEIDON_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_POSEIDON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* NEOVERSE_POSEIDON_H */
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