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4e865bd290
Extract clock information for UART, MMC & Watchdog from the clock manager Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I42d3d4ceeaf45788d457472f6ddcd3fe099f0133
34 lines
734 B
C
34 lines
734 B
C
/*
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* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2019, Intel Corporation. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef AGX_PRIVATE_H
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#define AGX_PRIVATE_H
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#define AGX_MMC_REG_BASE 0xff808000
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#define EMMC_DESC_SIZE (1<<20)
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#define EMMC_INIT_PARAMS(base, clk) \
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{ .bus_width = MMC_BUS_WIDTH_4, \
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.clk_rate = (clk), \
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.desc_base = (base), \
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.desc_size = EMMC_DESC_SIZE, \
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.flags = 0, \
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.reg_base = AGX_MMC_REG_BASE \
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}
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typedef enum {
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BOOT_SOURCE_FPGA = 0,
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BOOT_SOURCE_SDMMC,
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BOOT_SOURCE_NAND,
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BOOT_SOURCE_RSVD,
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BOOT_SOURCE_QSPI
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} boot_source_type;
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void enable_nonsecure_access(void);
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void socfpga_io_setup(int boot_source);
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#endif
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