mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
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39f5e27820
Implement stub functions for the EMI driver to ensure that the build can pass when a prebuilt library is not available. Change-Id: I296945a3df6766a3a133cd385a1e5038ca979403 Signed-off-by: Gavin Liu <gavin.liu@mediatek.corp-partner.google.com>
238 lines
9.9 KiB
C
238 lines
9.9 KiB
C
/*
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* Copyright (c) 2024, Mediatek Inc. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef PLATFORM_DEF_H
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#define PLATFORM_DEF_H
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#include <arch.h>
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#include <plat/common/common_def.h>
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#include <arch_def.h>
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#define PLAT_PRIMARY_CPU (0x0)
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#define MT_GIC_BASE (0x0C400000)
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#define MCUCFG_BASE (0x0C000000)
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#define MCUCFG_REG_SIZE (0x50000)
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#define IO_PHYS (0x10000000)
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/* Aggregate of all devices for MMU mapping */
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#define MTK_DEV_RNG1_BASE (IO_PHYS)
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#define MTK_DEV_RNG1_SIZE (0x10000000)
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#define TOPCKGEN_BASE (IO_PHYS)
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/*******************************************************************************
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* AUDIO related constants
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******************************************************************************/
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#define AUDIO_BASE (IO_PHYS + 0x0a110000)
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/*******************************************************************************
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* APUSYS related constants
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******************************************************************************/
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#define APUSYS_BASE (IO_PHYS + 0x09000000)
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#define APU_MD32_SYSCTRL (IO_PHYS + 0x09001000)
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#define APU_MD32_WDT (IO_PHYS + 0x09002000)
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#define APU_LOGTOP (IO_PHYS + 0x09024000)
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#define APUSYS_CTRL_DAPC_RCX_BASE (IO_PHYS + 0x09030000)
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#define APU_REVISER (IO_PHYS + 0x0903C000)
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#define APU_RCX_UPRV_TCU (IO_PHYS + 0x09060000)
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#define APU_RCX_EXTM_TCU (IO_PHYS + 0x09061000)
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#define APU_CMU_TOP (IO_PHYS + 0x09067000)
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#define APUSYS_CE_BASE (IO_PHYS + 0x090B0000)
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#define APU_ARE_REG_BASE (IO_PHYS + 0x090B0000)
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#define APU_RCX_VCORE_CONFIG (IO_PHYS + 0x090E0000)
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#define APU_AO_CTRL (IO_PHYS + 0x090F2000)
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#define APU_SEC_CON (IO_PHYS + 0x090F5000)
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#define APUSYS_CTRL_DAPC_AO_BASE (IO_PHYS + 0x090FC000)
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#define APU_MBOX0 (0x4C200000)
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#define APU_MD32_TCM (0x4D000000)
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#define APU_MD32_TCM_SZ (0x50000)
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#define APU_MBOX0_SZ (0x100000)
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#define APU_INFRA_BASE (0x1002C000)
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#define APU_INFRA_SZ (0x1000)
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#define APU_RESERVE_MEMORY (0x95000000)
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#define APU_SEC_INFO_OFFSET (0x100000)
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#define APU_RESERVE_SIZE (0x1400000)
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/*******************************************************************************
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* SPM related constants
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******************************************************************************/
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#define SPM_BASE (IO_PHYS + 0x0C004000)
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/*******************************************************************************
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* GPIO related constants
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******************************************************************************/
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#define GPIO_BASE (IO_PHYS + 0x0002D000)
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#define RGU_BASE (IO_PHYS + 0x0C00B000)
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#define DRM_BASE (IO_PHYS + 0x0000D000)
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#define IOCFG_RT_BASE (IO_PHYS + 0x02000000)
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#define IOCFG_RM1_BASE (IO_PHYS + 0x02020000)
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#define IOCFG_RM2_BASE (IO_PHYS + 0x02040000)
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#define IOCFG_RB_BASE (IO_PHYS + 0x02060000)
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#define IOCFG_BM1_BASE (IO_PHYS + 0x02820000)
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#define IOCFG_BM2_BASE (IO_PHYS + 0x02840000)
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#define IOCFG_BM3_BASE (IO_PHYS + 0x02860000)
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#define IOCFG_LT_BASE (IO_PHYS + 0x03000000)
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#define IOCFG_LM1_BASE (IO_PHYS + 0x03020000)
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#define IOCFG_LM2_BASE (IO_PHYS + 0x03040000)
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#define IOCFG_LB1_BASE (IO_PHYS + 0x030f0000)
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#define IOCFG_LB2_BASE (IO_PHYS + 0x03110000)
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#define IOCFG_TM1_BASE (IO_PHYS + 0x03800000)
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#define IOCFG_TM2_BASE (IO_PHYS + 0x03820000)
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#define IOCFG_TM3_BASE (IO_PHYS + 0x03860000)
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/*******************************************************************************
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* UART related constants
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******************************************************************************/
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#define UART0_BASE (IO_PHYS + 0x06000000)
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#define UART_BAUDRATE (115200)
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/*******************************************************************************
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* Infra IOMMU related constants
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******************************************************************************/
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#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
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#define INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00404000)
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#define PERICFG_AO_BASE (IO_PHYS + 0x06630000)
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#define PERICFG_AO_REG_SIZE (0x1000)
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/*******************************************************************************
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* GIC-600 & interrupt handling related constants
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******************************************************************************/
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/* Base MTK_platform compatible GIC memory map */
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#define BASE_GICD_BASE (MT_GIC_BASE)
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#define MT_GIC_RDIST_BASE (MT_GIC_BASE + 0x40000)
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#define MTK_GIC_REG_SIZE 0x400000
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/*******************************************************************************
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* MM IOMMU & SMI related constants
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******************************************************************************/
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#define SMI_LARB_0_BASE (IO_PHYS + 0x0c022000)
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#define SMI_LARB_1_BASE (IO_PHYS + 0x0c023000)
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#define SMI_LARB_2_BASE (IO_PHYS + 0x0c102000)
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#define SMI_LARB_3_BASE (IO_PHYS + 0x0c103000)
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#define SMI_LARB_4_BASE (IO_PHYS + 0x04013000)
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#define SMI_LARB_5_BASE (IO_PHYS + 0x04f02000)
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#define SMI_LARB_6_BASE (IO_PHYS + 0x04f03000)
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#define SMI_LARB_7_BASE (IO_PHYS + 0x04e04000)
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#define SMI_LARB_9_BASE (IO_PHYS + 0x05001000)
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#define SMI_LARB_10_BASE (IO_PHYS + 0x05120000)
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#define SMI_LARB_11A_BASE (IO_PHYS + 0x05230000)
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#define SMI_LARB_11B_BASE (IO_PHYS + 0x05530000)
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#define SMI_LARB_11C_BASE (IO_PHYS + 0x05630000)
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#define SMI_LARB_12_BASE (IO_PHYS + 0x05340000)
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#define SMI_LARB_13_BASE (IO_PHYS + 0x06001000)
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#define SMI_LARB_14_BASE (IO_PHYS + 0x06002000)
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#define SMI_LARB_15_BASE (IO_PHYS + 0x05140000)
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#define SMI_LARB_16A_BASE (IO_PHYS + 0x06008000)
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#define SMI_LARB_16B_BASE (IO_PHYS + 0x0600a000)
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#define SMI_LARB_17A_BASE (IO_PHYS + 0x06009000)
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#define SMI_LARB_17B_BASE (IO_PHYS + 0x0600b000)
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#define SMI_LARB_19_BASE (IO_PHYS + 0x0a010000)
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#define SMI_LARB_21_BASE (IO_PHYS + 0x0802e000)
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#define SMI_LARB_23_BASE (IO_PHYS + 0x0800d000)
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#define SMI_LARB_27_BASE (IO_PHYS + 0x07201000)
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#define SMI_LARB_28_BASE (IO_PHYS + 0x00000000)
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#define SMI_LARB_REG_RNG_SIZE (0x1000)
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/*******************************************************************************
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* APMIXEDSYS related constants
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******************************************************************************/
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#define APMIXEDSYS (IO_PHYS + 0x0000C000)
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/*******************************************************************************
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* VPPSYS related constants
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******************************************************************************/
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#define VPPSYS0_BASE (IO_PHYS + 0x04000000)
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#define VPPSYS1_BASE (IO_PHYS + 0x04f00000)
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/*******************************************************************************
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* VDOSYS related constants
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******************************************************************************/
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#define VDOSYS0_BASE (IO_PHYS + 0x0C01D000)
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#define VDOSYS1_BASE (IO_PHYS + 0x0C100000)
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/*******************************************************************************
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* DP related constants
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******************************************************************************/
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#define EDP_SEC_BASE (IO_PHYS + 0x2EC50000)
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#define DP_SEC_BASE (IO_PHYS + 0x2EC10000)
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#define EDP_SEC_SIZE (0x1000)
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#define DP_SEC_SIZE (0x1000)
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/*******************************************************************************
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* EMI MPU related constants
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*******************************************************************************/
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#define EMI_MPU_BASE (IO_PHYS + 0x00428000)
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#define SUB_EMI_MPU_BASE (IO_PHYS + 0x00528000)
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#define EMI_SLB_BASE (IO_PHYS + 0x0042e000)
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#define SUB_EMI_SLB_BASE (IO_PHYS + 0x0052e000)
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#define CHN0_EMI_APB_BASE (IO_PHYS + 0x00201000)
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#define CHN1_EMI_APB_BASE (IO_PHYS + 0x00205000)
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#define CHN2_EMI_APB_BASE (IO_PHYS + 0x00209000)
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#define CHN3_EMI_APB_BASE (IO_PHYS + 0x0020D000)
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#define EMI_APB_BASE (IO_PHYS + 0x00429000)
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#define INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00425000)
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#define NEMI_SMPU_BASE (IO_PHYS + 0x0042f000)
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#define SEMI_SMPU_BASE (IO_PHYS + 0x0052f000)
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#define SUB_EMI_APB_BASE (IO_PHYS + 0x00529000)
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#define SUB_INFRA_EMI_DEBUG_CFG_BASE (IO_PHYS + 0x00525000)
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#define SUB_INFRACFG_AO_MEM_BASE (IO_PHYS + 0x00504000)
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/*******************************************************************************
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* System counter frequency related constants
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******************************************************************************/
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#define SYS_COUNTER_FREQ_IN_HZ (13000000)
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#define SYS_COUNTER_FREQ_IN_MHZ (13)
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/*******************************************************************************
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* Generic platform constants
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******************************************************************************/
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#define PLATFORM_STACK_SIZE (0x800)
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#define SOC_CHIP_ID U(0x8196)
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/*******************************************************************************
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* Platform memory map related constants
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******************************************************************************/
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#define TZRAM_BASE (0x94600000)
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#define TZRAM_SIZE (0x00200000)
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/*******************************************************************************
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* BL31 specific defines.
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******************************************************************************/
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/*
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* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
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* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
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* little space for growth.
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*/
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#define BL31_BASE (TZRAM_BASE + 0x1000)
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#define BL31_LIMIT (TZRAM_BASE + TZRAM_SIZE)
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/*******************************************************************************
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
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#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
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#define MAX_XLAT_TABLES (128)
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#define MAX_MMAP_REGIONS (512)
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/*******************************************************************************
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* CPU PM definitions
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*******************************************************************************/
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#define PLAT_CPU_PM_B_BUCK_ISO_ID (6)
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#define PLAT_CPU_PM_ILDO_ID (6)
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#define CPU_IDLE_SRAM_BASE (0x11B000)
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#define CPU_IDLE_SRAM_SIZE (0x1000)
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/*******************************************************************************
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* SYSTIMER related definitions
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******************************************************************************/
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#define SYSTIMER_BASE (0x1C400000)
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#endif /* PLATFORM_DEF_H */
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