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4c700c1563
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
51 lines
2.1 KiB
C
51 lines
2.1 KiB
C
/*
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* Copyright (c) 2019-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef NEOVERSE_V1_H
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#define NEOVERSE_V1_H
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#define NEOVERSE_V1_MIDR U(0x410FD400)
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/* Neoverse V1 loop count for CVE-2022-23960 mitigation */
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#define NEOVERSE_V1_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V1_CPUECTLR_EL1 S3_0_C15_C1_4
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#define NEOVERSE_V1_CPUPSELR_EL3 S3_6_C15_C8_0
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#define NEOVERSE_V1_CPUPOR_EL3 S3_6_C15_C8_2
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#define NEOVERSE_V1_CPUPMR_EL3 S3_6_C15_C8_3
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#define NEOVERSE_V1_CPUPCR_EL3 S3_6_C15_C8_1
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
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#define NEOVERSE_V1_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
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#define NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV ULL(3)
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#define CPUECTLR_EL1_PF_MODE_LSB U(6)
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#define CPUECTLR_EL1_PF_MODE_WIDTH U(2)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define NEOVERSE_V1_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define NEOVERSE_V1_ACTLR2_EL1 S3_0_C15_C1_1
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_0 ULL(1)
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_2 (ULL(1) << 2)
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_28 (ULL(1) << 28)
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#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
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#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
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#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47)
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#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0
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#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55)
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#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56)
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#endif /* NEOVERSE_V1_H */
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