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c7e698cfde
Cortex-X3 erratum 2615812 is a Cat B erratum that applies to revisions r0p0, r1p0, and r1p1, and is still open. The workaround is to disable the use of the Full Retention power mode in the core (setting WFI_RET_CTRL and WFE_RET_CTRL in CORTEX_X3_IMP_CPUPWRCTLR_EL1 to 0b000). SDEN can be found here: https://developer.arm.com/documentation/SDEN2055130/latest Change-Id: I5ad66df3e18fc85a6b23f6662239494ee001d82f Signed-off-by: Harrison Mutai <harrison.mutai@arm.com>
34 lines
1.3 KiB
C
34 lines
1.3 KiB
C
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_X3_H
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#define CORTEX_X3_H
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#define CORTEX_X3_MIDR U(0x410FD4E0)
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/* Cortex-X3 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_X3_BHB_LOOP_COUNT U(132)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_X3_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_X3_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#define CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT U(4)
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#define CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT U(7)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
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#endif /* CORTEX_X3_H */
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