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4c700c1563
Align entire TF-A to use Arm in copyright header. Change-Id: Ief9992169efdab61d0da6bd8c5180de7a4bc2244 Signed-off-by: Govindraj Raja <govindraj.raja@arm.com>
45 lines
1.7 KiB
C
45 lines
1.7 KiB
C
/*
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* Copyright (c) 2016-2019, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A73_H
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#define CORTEX_A73_H
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#include <lib/utils_def.h>
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/* Cortex-A73 midr for revision 0 */
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#define CORTEX_A73_MIDR U(0x410FD090)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A73_CPUECTLR_EL1 S3_1_C15_C2_1 /* Instruction def. */
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#define CORTEX_A73_CPUECTLR_SMP_BIT (ULL(1) << 6)
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/*******************************************************************************
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* L2 Memory Error Syndrome register specific definitions.
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******************************************************************************/
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#define CORTEX_A73_L2MERRSR_EL1 S3_1_C15_C2_3 /* Instruction def. */
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/*******************************************************************************
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* CPU implementation defined register specific definitions.
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******************************************************************************/
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#define CORTEX_A73_IMP_DEF_REG1 S3_0_C15_C0_0
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#define CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE (ULL(1) << 3)
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#define CORTEX_A73_DIAGNOSTIC_REGISTER S3_0_C15_C0_1
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#define CORTEX_A73_IMP_DEF_REG2 S3_0_C15_C0_2
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/*******************************************************************************
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* Helper function to access a73_cpuectlr_el1 register on Cortex-A73 CPUs
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******************************************************************************/
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#ifndef __ASSEMBLER__
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DEFINE_RENAME_SYSREG_RW_FUNCS(a73_cpuectlr_el1, CORTEX_A73_CPUECTLR_EL1)
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#endif /* __ASSEMBLER__ */
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#endif /* CORTEX_A73_H */
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