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888eafa00b
Cortex-A710 erratum 2291219 is a Cat B erratum that applies to revisions r0p0, r1p0, and r2p0, and is fixed in r2p1. The workaround is to set CPUACTLR2_EL1[36] to 1 before the power down sequence that sets CORE_PWRDN_EN. This allows the cpu to retry the power down and prevents the deadlock. TF-A never clears this bit even if it wakes up from the wfi in the sequence since it is not expected to do anything but retry to power down after and the bit is cleared on reset. SDEN can be found here: https://developer.arm.com/documentation/SDEN1775101/latest Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com> Change-Id: I7d3a97dfac0c433c0be386c1f3d2f2e895a3f691
65 lines
3 KiB
C
65 lines
3 KiB
C
/*
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* Copyright (c) 2021-2022, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A710_H
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#define CORTEX_A710_H
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#define CORTEX_A710_MIDR U(0x410FD470)
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/* Cortex-A710 loop count for CVE-2022-23960 mitigation */
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#define CORTEX_A710_BHB_LOOP_COUNT U(32)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_A710_CPUECTLR_EL1 S3_0_C15_C1_4
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#define CORTEX_A710_CPUECTLR_EL1_PFSTIDIS_BIT (ULL(1) << 8)
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A710_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A710_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR_EL1 S3_0_C15_C1_0
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#define CORTEX_A710_CPUACTLR_EL1_BIT_46 (ULL(1) << 46)
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#define CORTEX_A710_CPUACTLR_EL1_BIT_22 (ULL(1) << 22)
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/*******************************************************************************
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* CPU Auxiliary Control register 2 specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR2_EL1 S3_0_C15_C1_1
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#define CORTEX_A710_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
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#define CORTEX_A710_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
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/*******************************************************************************
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* CPU Auxiliary Control register 5 specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUACTLR5_EL1 S3_0_C15_C8_0
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
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#define CORTEX_A710_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
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/*******************************************************************************
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* CPU Auxiliary Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUECTLR2_EL1 S3_0_C15_C1_5
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#define CORTEX_A710_CPUECTLR2_EL1_PF_MODE_CNSRV ULL(9)
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#define CPUECTLR2_EL1_PF_MODE_LSB U(11)
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#define CPUECTLR2_EL1_PF_MODE_WIDTH U(4)
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/*******************************************************************************
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* CPU Selected Instruction Private register specific definitions.
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******************************************************************************/
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#define CORTEX_A710_CPUPSELR_EL3 S3_6_C15_C8_0
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#define CORTEX_A710_CPUPCR_EL3 S3_6_C15_C8_1
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#define CORTEX_A710_CPUPOR_EL3 S3_6_C15_C8_2
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#define CORTEX_A710_CPUPMR_EL3 S3_6_C15_C8_3
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#endif /* CORTEX_A710_H */
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